SLVAFZ0 November   2024 DRV8161 , DRV8162

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Three-Phase Gate Driver
    1. 2.1 Architecture
    2. 2.2 Layout Considerations
      1. 2.2.1 Advantages
        1. 2.2.1.1 MCU to DRV Signal Routing
        2. 2.2.1.2 Component Reduction
      2. 2.2.2 Challenges
        1. 2.2.2.1 MOSFET Placement
    3. 2.3 Typical Applications
  6. 3Half-Bridge (Single Phase) Gate Driver
    1. 3.1 Architecture
    2. 3.2 Layout Considerations
      1. 3.2.1 Advantages
        1. 3.2.1.1 MOSFET Placement
        2. 3.2.1.2 Independent Control
        3. 3.2.1.3 Ease of Replacement
      2. 3.2.2 Challenges
        1. 3.2.2.1 Longer Routing Between Gate Driver and Micro Controller
        2. 3.2.2.2 Additional Component Requirements
    3. 3.3 Typical Applications
  7. 4Summary
  8. 5References

2.2.2.1 MOSFET Placement

In motor driver board design, the most critical signals are the gate and source signals of MOSFET as these signals are crucial for efficient commutation. Minimizing the distance between the driver and the MOSFET for gate and source signals are needed to reduce the effects of trace inductance. Figure 2-2 shows how power stage design adds parasitic inductance in gate source signals.

Since the gate and source signals for all three phases are leaving the same driver, there is a challenge to place the half-bridges close, due to components size. This becomes more critical when the boards have space restrictions.

These routing challenges lead to

  • Signal integrity issues:

    Another challenge in motor layout arises when the 3 half-bridges are not placed in roughly same distance or via similar trace paths from the driver. This can result in phase to phase deviation in turn on/off times of the MOSFETs or differences in measured phase current through CSA.

    Long gate traces can also result in absolute maximum violation of the driver (either overshoot or undershoot) due to the added inductance.

  • Source node transients:

    Switch-node ringing is an LC oscillation on the switch-node due to the parasitics of the PCB and power MOSFETs. Switch-node ringing causes EMI and creates overshoot and undershoot voltages. These transients can violate the absolute maximum ratings of the MOSFET drain-to-source voltage and the gate driver pins. This also can decrease the efficiency of the power stage.

    The longer trace paths can also add a parasitic impedance between GND of gate driver device and GND of power MOSFETs. The parasitic impedance can cause a GND shift between device and source of low-side MOSFETs and can lead to similar challenges for source node transient described above.

Note:

The circular PCB shown in Figure 2-2 and Figure 3-4 are common designs used in power tools and E-bike designs, where a PCB is mounted on top of the motor. This design was chosen to highlight the effects of MOSFET placement and trace inductance, but the principle applies to all board shapes and sizes.

Three-Phase Gate Driver Implementation Showing Effects of Transients on Gate and Source signal due to Effects of Trace InductanceFigure 2-2 Three-Phase Gate Driver Implementation Showing Effects of Transients on Gate and Source signal due to Effects of Trace Inductance