SLVK182 December   2024 DRV8351-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Bias Diagram
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
  7. 4Reference Documents
  8. 5Appendix: HDR TID Report Data
  9. 6Appendix: ELDRS TID Report Data

1 Device Information

The DRV8351-SEP is a radiation-hardness-assured (RHA) 40V three half-bridge gate drivers, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8351-SEP generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the highside MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750mA source and 1.5A sink currents. The driver features:

  • Absolute Maximum Voltage ratings
    • PVDD = 42.5V
    • GVDD = 15V
  • Approximately 125ns propagation delay
  • Approximately 4.0ns high-side and low-side matching
  • 3x PWM Mode
    • 3x PWM allows for outputs to be controlled by dedicated input
    • PWM allows for two complementary outputs signals to be generated from single input