SLVSAR1E January   2011  – July 2015 DRV8833

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Motor Drivers
      2. 7.3.2 Bridge Control and Decay Modes
      3. 7.3.3 Current Control
      4. 7.3.4 nSLEEP Operation
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Thermal Shutdown (TSD)
        3. 7.3.5.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Motor Current Trip Point
        3. 8.2.2.3 Sense Resistor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supply and Logic Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Heatsinking
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Maximum Output Current
      2. 10.3.2 Thermal Protection
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7 Detailed Description

7.1 Overview

The DRV8833 device is an integrated motor driver solution for brushed DC or bipolar stepper motors. The device integrates two NMOS H-bridges and current regulation circuitry. The DRV8833 can be powered with a supply voltage from 2.7 to 10.8 V and can provide an output current up to 1.5-A RMS.

A simple PWM interface allows easy interfacing to the controller circuit.

The current regulation is a fixed frequency PWM slow decay.

The device includes a low-power sleep mode, which lets the system save power when not driving the motor.

7.2 Functional Block Diagram

DRV8833 fbd2_lvsar1.gif

7.3 Feature Description

7.3.1 Fixed-Frequency PWM Motor Drivers

DRV8833 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 5 shows a block diagram of the circuitry.

DRV8833 motor_circuitry_lvsar1.gifFigure 5. Motor Control Circuitry

7.3.2 Bridge Control and Decay Modes

The AIN1 and AIN2 input pins control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1 and BIN2 input pins control the state of the BOUT1 and BOUT2 outputs. Table 1 shows the logic.

Table 1. H-Bridge Logic

xIN1 xIN2 xOUT1 xOUT2 FUNCTION
0 0 Z Z Coast/fast decay
0 1 L H Reverse
1 0 H L Forward
1 1 L L Brake/slow decay

The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states: fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted.

To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow decay, one xIN pin is held high.

Table 2. PWM Control of Motor Speed

xIN1 xIN2 FUNCTION
PWM 0 Forward PWM, fast decay
1 PWM Forward PWM, slow decay
0 PWM Reverse PWM, fast decay
PWM 1 Reverse PWM, slow decay

Figure 6 shows the current paths in different drive and decay modes.

DRV8833 decay_modes_lvsar1.gifFigure 6. Drive and Decay Modes

7.3.3 Current Control

The current through the motor windings may be limited, or controlled, by a fixed-frequency PWM current regulation, or current chopping. For DC motors, current control is used to limit the start-up and stall current of the motor. For stepper motors, current control is often used at all times.

When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Immediately after the current is enabled, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins with a reference voltage. The reference voltage is fixed at 200 mV.

The chopping current is calculated in Equation 1.

Equation 1. DRV8833 eq1_ichop_lvsar1.gif

Example: If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA.

Once the chopping current threshold is reached, the H-bridge switches to slow decay mode. Winding current is recirculated by enabling both of the low-side FETs in the bridge. This state is held until the beginning of the next fixed-frequency PWM cycle.

If current control is not needed, the xISEN pins should be connected directly to ground.

7.3.4 nSLEEP Operation

Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (up to 1 ms) needs to pass before the motor driver becomes fully operational. To make the board design simple, the nSLEEP can be pulled up to the supply (VM). TI recommends using a pullup resistor when this is done. This resistor limits the current to the input in case VM is higher than 6.5 V. Internally, the nSLEEP pin has a 500-kΩ resistor to GND. It also has a clamping Zener diode that clamps the voltage at the pin at 6.5 V. Currents greater than 250 µA can cause damage to the input structure. Hence the recommended pullup resistor would be between 20 kΩ and
75 kΩ.

7.3.5 Protection Circuits

The DRV8833 is fully protected against undervoltage, overcurrent and overtemperature events.

7.3.5.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (tOCP) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally.

Overcurrent conditions are detected independently on both high- and low-side devices; that is, a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for PWM current control, so it functions even without presence of the xISEN resistors.

7.3.5.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level, operation will automatically resume.

7.3.5.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. nFAULT is driven low in the event of an undervoltage condition.

Table 3. Device Protection

FAULT CONDITION ERROR REPORT H-BRIDGE INTERNAL CIRCUITS RECOVERY
VM undervoltage (UVLO) VM < 2.5 V None Disabled Disabled VM > 2.7 V
Overcurrent (OCP) IOUT > IOCP FAULTn Disabled Operating OCP
Thermal Shutdown (TSD) TJ > TTSD FAULTn Disabled Operating TJ < TTSD – THYS

7.4 Device Functional Modes

The DRV8833 is active unless the nSLEEP pin is brought logic low. In sleep mode, the H-bridge FETs are disabled (Hi-Z). The DRV8833 is brought out of sleep mode automatically if nSLEEP is brought logic high. tWAKE must elapse before the outputs change state after wakeup.

Table 4. Modes of Operation

FAULT CONDITION H-BRIDGE INTERNAL CIRCUITS
Operating nSLEEP pin high Operating Operating
Sleep mode nSLEEP pin low Disabled Disabled
Fault encountered Any fault condition met Disabled See Table 3