SLVSBC4G May   2012  – June 2017 TPS65381-Q1

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Typical Application Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 VDD6 Buck Switch-Mode Power Supply
      2. 5.3.2 VDD5 Linear Regulator
      3. 5.3.3 VDD3/5 Linear Regulator
      4. 5.3.4 VDD1 Linear Regulator
      5. 5.3.5 VSOUT1 Linear Regulator
      6. 5.3.6 Charge Pump
      7. 5.3.7 Wake-Up
      8. 5.3.8 Reset Extension
    4. 5.4 Device Functional Modes
      1. 5.4.1  Power-Up and Power-Down Behavior
      2. 5.4.2  Safety Functions and Diagnostics Overview
      3. 5.4.3  Voltage Monitor (VMON)
      4. 5.4.4  TPS65381-Q1 Internal Error Signals
      5. 5.4.5  Loss-of-Clock Monitor (LCMON)
      6. 5.4.6  Analog Built-In Self-Test (ABIST)
      7. 5.4.7  Logic Built-In Self-Test (LBIST)
      8. 5.4.8  Junction Temperature Monitoring and Current Limiting
      9. 5.4.9  Diagnostic MUX and Diagnostic Output Pin (DIAG_OUT)
        1. 5.4.9.1 Analog MUX (AMUX)
        2. 5.4.9.2 Digital MUX (DMUX)
        3. 5.4.9.3 Diagnostic MUX Output State (by MUX_OUT bit)
        4. 5.4.9.4 MUX Interconnect Check
      10. 5.4.10 Watchdog Timer (WD)
      11. 5.4.11 Watchdog Fail Counter, Status, and Fail Event
      12. 5.4.12 Watchdog Sequence
      13. 5.4.13 MCU to Watchdog Synchronization
      14. 5.4.14 Trigger Mode (Default Mode)
      15. 5.4.15 Q&A Mode
        1. 5.4.15.1 Watchdog Q&A Related Definitions
        2. 5.4.15.2 Watchdog Sequence in Q&A Mode
        3. 5.4.15.3 Question (Token) Generation
        4. 5.4.15.4 Answer Comparison and Reference Answer
          1. 5.4.15.4.1 Sequence of the 2-bit Watchdog Answer Counter
        5. 5.4.15.5 Watchdog Q&A Mode Sequence Events and WD_STATUS Register Updates
      16. 5.4.16 MCU Error Signal Monitor (MCU ESM)
        1. 5.4.16.1 TMS570 Mode
        2. 5.4.16.2 PWM Mode
      17. 5.4.17 Device Configuration Register Protection
      18. 5.4.18 Enable and Reset Driver Circuit
      19. 5.4.19 Device Operating States
      20. 5.4.20 STANDBY State
      21. 5.4.21 RESET State
      22. 5.4.22 DIAGNOSTIC State
      23. 5.4.23 ACTIVE State
      24. 5.4.24 SAFE State
      25. 5.4.25 State Transition Priorities
      26. 5.4.26 Power on Reset (NPOR)
    5. 5.5 Register Maps
      1. 5.5.1 Serial Peripheral Interface (SPI)
        1. 5.5.1.1 SPI Command Transfer Phase
        2. 5.5.1.2 SPI Data-Transfer Phase
        3. 5.5.1.3 Device Status Flag Byte Response
        4. 5.5.1.4 Device SPI Data Response
        5. 5.5.1.5 SPI Frame Overview
      2. 5.5.2 SPI Register Write Access Lock (SW_LOCK command)
      3. 5.5.3 SPI Registers (SPI Mapped Response)
        1. 5.5.3.1 Device Revision and ID
          1. 5.5.3.1.1 DEV_REV Register
          2. 5.5.3.1.2 DEV_ID Register
        2. 5.5.3.2 Device Status
          1. 5.5.3.2.1 DEV_STAT Register
        3. 5.5.3.3 Device Configuration
          1. 5.5.3.3.1 DEV_CFG1 Register
          2. 5.5.3.3.2 DEV_CFG2 Register
      4. 5.5.4 Device Safety Status and Control Registers
        1. 5.5.4.1  VMON_STAT_1 Register
        2. 5.5.4.2  VMON_STAT_2 Register
        3. 5.5.4.3  SAFETY_STAT_1 Register
        4. 5.5.4.4  SAFETY_STAT_2 Register
        5. 5.5.4.5  SAFETY_STAT_3 Register
        6. 5.5.4.6  SAFETY_STAT_4 Register
        7. 5.5.4.7  SAFETY_STAT_5 Register
        8. 5.5.4.8  SAFETY_ERR_CFG Register
        9. 5.5.4.9  SAFETY_BIST_CTRL Register
        10. 5.5.4.10 SAFETY_CHECK_CTRL Register
        11. 5.5.4.11 SAFETY_FUNC_CFG Register
        12. 5.5.4.12 SAFETY_ERR_STAT Register
        13. 5.5.4.13 SAFETY_ERR_PWM_H Register
        14. 5.5.4.14 SAFETY_ERR_PWM_L Register
        15. 5.5.4.15 SAFETY_PWD_THR_CFG Register
        16. 5.5.4.16 SAFETY_CFG_CRC Register
        17. 5.5.4.17 Diagnostics
          1. 5.5.4.17.1 DIAG_CFG_CTRL Register
          2. 5.5.4.17.2 DIAG_MUX_SEL Register
      5. 5.5.5 Watchdog Timer
        1. 5.5.5.1 WD_TOKEN_FDBK Register
        2. 5.5.5.2 WD_WIN1_CFG Register
        3. 5.5.5.3 WD_WIN2_CFG Register
        4. 5.5.5.4 WD_TOKEN_VALUE Register
        5. 5.5.5.5 WD_STATUS Register
        6. 5.5.5.6 WD_ANSWER Register
      6. 5.5.6 Sensor Supply
        1. 5.5.6.1 SENS_CTRL Register
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 VDD6 Preregulator
        2. 6.2.2.2 VDD1 Linear Controller
        3. 6.2.2.3 VSOUT1 Tracking Linear Regulator, Configured to Track VDD5
        4. 6.2.2.4 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 6-V Output Tracking VDD3/5 In 3.3-V Mode
        5. 6.2.2.5 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 9-V Output Tracking to 5-V Input from VDD5
        6. 6.2.2.6 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured in Non-tracking Mode Providing a 4.5-V Output
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 VDD6 Buck Preregulator
      2. 8.1.2 VDD1 Linear Regulator Controller
      3. 8.1.3 VDD5 and VDD3/5 Linear Regulators
      4. 8.1.4 VSOUT1 Tracking Linear Regulator
      5. 8.1.5 Charge Pump
      6. 8.1.6 Other Considerations
    2. 8.2 Layout Example
    3. 8.3 Power Dissipation and Thermal Considerations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

2 Revision History

Changes from F Revision (May 2016) to G Revision

  • Changed the Features list for Supply rails to show output current instead of current limit. Added general current limit bullet in the FEATURES listGo
  • Added acronym definitions Go
  • Changed the PIN Function table descriptions to clarify device operation Go
  • Changed the max value for the charge-pump voltages from 52 V to lesser of VBATP + 16V or 52 V with footnote in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Changed M1.12 and M1.13 Sensor supply feedback and supply voltage by combining in M1.12 with conditions of use for the Sensor supply output and feedback voltage to match how the sensor supply is used. Changed the maximum to 18 V in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted M1.13 Sensor supply output voltage by combining with M1.12 in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Changed the table note for Absolute Maximum Ratings Go
  • Changed changed recommended operating condition descriptions for R1.1, R1.2 and R1.3 to make the operation of device more clear in the Recommended Operating ConditionsGo
  • Deleted recommended operating condition R1.3a and R1.3b, VBAT_SAFING impact to device operation was included in R1.2 and R1.3 to make the operation of device more clear in the Recommended Operating ConditionsGo
  • Changed link formats throughout documentGo
  • Changed recommended maximum voltage for VBATP and VBAT_SAFING in the Recommended Operating Conditions table Go
  • Changed the Thermal Metric table and Derating Profile for Power Dissipation Based on High-K JEDEC PCB in the Thermal Information section.Go
  • Changed application report linkGo
  • Changed the Derating Profile for the Power Dissipation in the Thermal Information table and the Power Dissipation and Thermal Considerations section Go
  • Deleted R1.3b from the operating conditions in the Electrical Characteristics section since VBAT_SAFING condition R1.3b was merged with R1.2 in the Recommended Operating Conditions, Timing Requirements and Switching Characteristics sections Go
  • Changed VDD6, POS 1.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted Hysteresis parameter from TprotVDD6 (POS 1.7) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed VDD5, POS 2.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed POS 2.3 test condition to Load step 20% to 80% in 5 µs, with CVDD5 = 5 µF for VDD5 output voltage dynamic parameter in the Electrical Characteristics tableGo
  • Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 2.6Go
  • Deleted Hysteresis parameter from TprotVDD5 (POS 2.13) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed VDD3/5, POS 3.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed POS 3.3 into 3.3a for 3.3 V setting and 3.3v for 5 V setting for VDD3/5 output voltage dynamic parameter in the Electrical Characteristics tableGo
  • Changed POS 3.3a and 3.3b test condition to Load step 20% to 80% in 5 µs, with CVDD3/5 = 5 µF for VDD3/5 output voltage dynamic parameter in the Electrical Characteristics tableGo
  • Changed the minimum for POS 3.3a from 3.17 V to 3.15 V, VDD3/5 output voltage dynamic parameter in the Electrical Characteristics tableGo
  • Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 3.6Go
  • Deleted Hysteresis parameter from TprotVDD3/5 (POS 3.13) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed MAX value of VDD1SENSE(4.2) from 0.816 mV to 0.808 mV in the Electrical Characteristics table Go
  • Changed VDD1SENSE POS 4.2 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed VDD1dyn, POS 4.7, to typical due to dependency on external FET choice in the Electrical Characteristics table Go
  • Changed the VDD1max, POS 4.8, to specific VDD1 output voltage range for test condition in the Electrical Characteristics table Go
  • Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 4.9Go
  • Changed MVVSOUT1 min and max values from –25 and 25 to –35 and 35 in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed VSFB1, POS 5.3 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed Test Condition and PSRR to > 40 dB typical sensor supply to clarify the test in the Electrical Characteristics for parameters 5.6Go
  • Changed POS 5.11, VSOUT1SH, for clarity of condition for output short circuit voltage range and changed maximum voltage to 18 V in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted Hysteresis parameter from TprotVSOUT1 (POS 5.13) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed IVSOUT1_limit, POS 5.14 minimum from 100 mA to 120 mA in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed min value for VDD3/5_UVhead to 155 mV from 170 mV for 3.3-V setting in the ELECTRICAL CHARACTERISTICS table POS 6.13Go
  • Changed VDD_UV POS 6.16 units from ratio to mV for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed VDD1_OV POS 6.17 MIN from 824 mV to 816 mV in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed VDD1_OV POS 6.17 units from ratio to mV for consistency in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted VSOUT1_UV hysteresis parameter (typical), POS 6.19a in the ELECTRICAL CHARACTERISTICS table.Go
  • Deleted VSOUT1_OV hysteresis parameter (typical), POS 6.20a in the ELECTRICAL CHARACTERISTICS table.Go
  • Changed I_IGN_rev parameter (7.4), -1, from MAX to MIN to match polarity in the ELECTRICAL CHARACTERISTICS table Go
  • Changed I_CAN_rev parameter (7.8), -1, from MAX to MIN to match polarity in the ELECTRICAL CHARACTERISTICS table Go
  • Added clarification to POS 10.1, 10.2 and 10.3 by using pin names in parameter field instead of footnote and adding SEL_VDD3/5 pin to 10.1 and 10.2 in the ELECTRICAL CHARACTERISTICS table Go
  • Changed all references of VDD3_5 to VDD3/5 for consistency in the datasheet Go
  • Added clarification on VDD6 current limit and duty cycle in the Electrical Characteristics sectionGo
  • Added clarification on IVDD3/5 load current at power up in the Electrical Characteristics sectionGo
  • Added clarification on IVSOUT1 load current and power dissipation in the Electrical Characteristics sectionGo
  • Added clarification on IVDD5_limit current limit in the Electrical Characteristics sectionGo
  • Added clarification on IVDD3/5_limit current limits in the Electrical Characteristics sectionGo
  • Changed tdelayVDD5 max from 2.5 ms to 5 ms in the Timing Requirements table Go
  • Changed tdelayVDD3/5 max from 2.5 ms to 5 ms in the Timing Requirements table Go
  • Changed tdelayVDD1 max from 2.5 ms to 5 ms in the Timing Requirements table Go
  • Changed VBATP_deglitch minimum from 200 µs to 180 µs and maximum from 280 µs to 260 µs in the Timing Requirements table for POS 6.7.Go
  • Changed minimum for tWD_pulse in the ELECTRICAL CHARACTERISTICS table to 14.25 µs from 28 µsGo
  • Deleted tERROR_WDI_deglitch in the ELECTRICAL CHARACTERISTICS µsGo
  • Changed min value for thigh(13.3) to 85.7 ns in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed format of graph Go
  • Added clarification of operation in the VDD6 Buck Switch Mode Power Supply section Go
  • Added a note to the VSOUT1 register clarifying VSOUT1_EN through RESET state in the VSOUT1 Linear Regulator sectionGo
  • Added note in the Wake-Up section to not send WR_CAN_STBY command while CANWU and/or IGN are still high.Go
  • Changed WDT_FAIL_CNT and WD_FAIL_CNT to WD_FAIL_CNT[2:0] throughout document Go
  • Changed section heading levels from 5.4.1.1 through 5.4.1.20Go
  • Changed the VCP17_OV impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. Go
  • Changed the VCP12_OV the impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. Go
  • Changed the MAIN_BG and VMON_BG UV and OV impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. Go
  • Changed all _UVN Signal Names in the Internal Error Signals table and Digital MUX section to Nxxx_UV for consistency in datasheet for inverted logic signal names with N at the beginning of the name.Go
  • Changed the signal name from VCP_OV to VCP17_OV for D1.7 in the Internal Error Signals table. Also changed the device state from Not changed for NRES and ENDRV to LOW, and State to STANDBY Go
  • Changed the max deglitch for VDD5_OT, VDD3/5_OT and VSOUT1_OT to 64us in the Internal Error Signals table Go
  • Changed the naming convention of EN_VDD5_OT and EN_VDD3/5_OT to NMASK_VDD5_OT and NMASK_VDD3/5_OT to clarify option of these configuration bits throughout the datasheet Go
  • Changed the description of VDD5_OT in the Internal Error Signals table for clarity Go
  • Changed the VMON_TRIM_ERR deglitch time minimum from 15 to 5 µs and maximum from 30 to 10 µs in the Internal Error Signals table Go
  • Changed the VMON_TRIM_ERR device state when flag is set to NRES = LOW from not changed, ENDRV = LOW from not changed and Device State to STANDBY from not changed in the Internal Error Signals table Go
  • Added clarification footnote to VDD5_CL internal signal in the Internal Error Signals table Go
  • Changed Analog BIST Run States diagram for to clarify operation in the Analog Built-In Self-Test sectionGo
  • Changed ABIST_UVOV_ERR and ABIST_OV_UV to ABIST_ERR throughout documentGo
  • Added notes to clarify considerations needed if a manual run of LBIST is done in DIAGNOSTIC or ACTIVE state in the Logic Built-In Self-Test (LBIST) sectionGo
  • Added clarification in the Analog Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) sections to clarify operation Go
  • Changed paragraphs for VSOUT1, VDD6 and VDD3/5 overtemperature and current limit in the Junction Temperature Monitoring and Current Limiting section to clarify device operationGo
  • Changed the descriptions in the Overtemperature and Overcurrent Protection Overview table to clarify device operation and made naming for thermal shutdown consistent to overtemperature Go
  • Changed Section title to Diagnostic MUX and Diagnostic Output Pin (DIAG_OUT)Go
  • Added clarity to the DIAG_OUT description in the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added clarification to the SPI Interface Note for the use of the SPI in a bus while DIAG_OUT MUX is enabled in the Diagnostic Output Pin DIAG_OUT sectionGo
  • Changed values and clarity of AMUX operation and added minimum output resistance in the Analog MUX Selection tableGo
  • Changed WDT_ signal names to WD_, WD_RES_EN toWD_RST_EN, NMASK_VDD1_OV to NMASK_VDD1_UV_OV, and EN_DRV to ENDRV throughout documentGo
  • Changed NRST_EXT_IN to NRES_EXT_IN for consistency with pin nameGo
  • Changed WDI/Error to Error/WDI throughout documentGo
  • Changed the Watchdog Question (Token) Generation image in the Watchdog Timer Configuration for Question and Answer Configuration sectionGo
  • Changed Figure for Watchdog Answer Calculation in the Question (Token) Generation section to remove FDBK[3:0] impact on Answer-x byte calculationGo
  • Changed TOKEN_ERR bit name to ANSWER_ERR to more accurately describe the error the bit indicates throughout the datasheet Go
  • Changed SEQ_ERR status bit in Table WD_STATUS Bits Versus Possible Watchdog Sequence Events sectionGo
  • Added a note to clarify impact of changing SAFETY_ERR_PWM_L or SAFETY_ERR_PWM_H while the MCU ESM is running in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added a note to clarify MCU ESM diagnostics in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added clarification in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added clarification for the LOW minimum and maximum duration time for the MCU ESM in the TMS570 Mode sectionGo
  • Changed the time range for HIGH and LOW pulse duration in PWM Mode section from 5 µs to 15 µs (minimum) and 1.28 ms to 3.8 ms (maximum) for consistency along with additional clarifications of operation Go
  • Added clarification for HIGH and LOW pulse register minimum and maximum pulse timing for the MCU ESM in the PWM Mode sectionGo
  • Added a note to clarify MCU ESM to MCU synchronization in the MCU Error Signal Monitor (MCU ESM) PWM Mode sectionGo
  • Added note to clarify uncleared CFG_CRC_ERR impact to state diagram during DIAGNOSTIC state in the list of steps in the Device Configuration Register Protection sectionGo
  • Changed the Reset and Enable Circuit image to clarify operationGo
  • Changed section title from Device Controller State Diagram to Device Operating States and clarified device operating states operationGo
  • Changed the STANDBY, RESET, DIAGNOSTIC, ACTIVE and SAFE state text descriptions in their sections to clarify device operation.Go
  • Added clarification in the RESET STATE listGo
  • Added clarification on BIST running on exit of RESET State to the RESET STATE sectionGo
  • Added note to clarify considerations needed if a manual run of LBIST is done in the DIAGNOSTIC state in the DIAGNOSTIC state sectionGo
  • Added note to clarify considerations needed if a manual run of LBIST is done in the ACTIVE state in the ACTIVE state sectionGo
  • Added note to clarify SAFE state time-out possible state transitions due to the SAFE state time-out in the SAFE state sectionGo
  • Added the Power on Reset (NPOR) section to clarify device operation.Go
  • Changed the STAT[2] and STAT[0] descriptions for SPI errors in the Device Status Flag Byte Response tableGo
  • Added note to explain additional SPI diagnostics in the Device Status Flag Byte Response sectionGo
  • Added SPI Register Write Access Lock (SW_LOCK command) section in the Register Map section Go
  • Added clarification on which registers are re-initialized to default values after LBIST run in Register Map section Go
  • Added clarification to WR_CAN_STBY that this command is only valid with data 00h in the SPI Command TableGo
  • Deleted note "SPI WR update can occur only in the DIAGNOSTIC and ACTIVE states" for WR_SAFETY_BIST_CTRL command in the SPI Command TableGo
  • Changed SAFE_CFG_CRC to SAFETY_CFG_CRC throughout the datasheet for consistency of the register name Go
  • Changed register bit descriptions in the DEV_CFG2 Register table to clarify device operation Go
  • Added clarification on VDD5_UV operation when VDD5_EN = 0 in the VMON_STAT_2 RegisterGo
  • Added clarity to note on VDD5_ILIM bit description in the SAFETY_STAT_1 Register tableGo
  • Changed the D[5] NRES_ERR, LBIST_ERR, ABIST_ERR, LBIST_RUN and ABIST_RUN register descriptions in SAFETY_STAT_3 RegisterGo
  • Added to the NRES_ERR description in the SAFETY_STAT_3 Register tableGo
  • Changed the SPI_ERR[1:0] description in the SAFETY_STAT_4 Register tableGo
  • Changed the LOCLK description in the SAFETY_STAT_4 Register tableGo
  • Changed MCU_ERR bit description inSAFETY_STAT_4 Register tableGo
  • Changed WD_ERR bit and NRES_ERR bit description inSAFETY_STAT_4 Register table to clarify operationGo
  • Deleted note "Write update can only occur in the DIAGNOSTIC and ACTIVE states." for WR_SAFETY_BIST_CTRL command in the SAFETY _BIST_CTRL RegisterGo
  • Changed SAFETY_STATUS_2 to SAFETY_STAT_2 for consistency in the datasheet Go
  • Changed NO_ERROR bit description to improve clarity in the SAFETY_CHECK_CTRL Register table Go
  • Changed ERROR_PIN_FAIL bit description in the SAFETY_ERR_STAT Register tableGo
  • Changed to clarity the WD_FAIL bit description in the SAFETY_ERR_STAT Register tableGo
  • Changed ERR_CNT to DEV_ERR_CNT[3:0] throughout datasheet for consistency in naming. Go
  • Added clarification on the TOKEN_SEED[3:0] to the description in the WD_TOKEN_FDBCK Register table Go
  • Changed WD_FAIL_TH description in the WDT_TOKEN_VALUE Register table for consistencyGo
  • Changed added clarification on clearing of the ANSWER_ERR bit in the WD_STATUS Register table Go
  • Deleted "This bit is set to 1 when switching between the Trigger and Q&A Mode" and added clarification on how to clear the WD_CFG_CHG bit description in the WD_STATUS Register table Go
  • Changed TIME_OUT bit description in the WD_STATUS Register table to clarify how the bit is cleared. Go
  • Added ANSWER_EARLY bit operation during trigger mode to the WD_STATUS Register table Go
  • Changed the description of VDD_EN in the SENS_CTRL Register tableGo
  • Changed the description of VSOUT1_EN in the SENS_CTRL Register tableGo
  • Clarified capacitors, resistor tolerance impact on regulation and monitoring in the Typical Application DiagramGo
  • Clarified resistor tolerance impact on regulation and monitoring in the VDD1 Linear Controller SectionGo
  • Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 6-V Output Tracking VDD3/5 In 3.3-V Mode SectionGo
  • Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 9-V Output Tracking to 5-V Input from VDD5 SectionGo
  • Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured in Non-tracking Mode Providing a 4.5-V Output SectionGo
  • Changed and clarified the System Examples drawingsGo
  • Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Q&A Mode flowchartGo
  • Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Trigger Mode flowchartGo
  • Added Power Dissipation and Thermal Considerations in the Layout sectionGo
  • Added Receiving Notification of Documentation Updates section Go
  • Changed the Electrostatic Discharge Caution statementGo

Changes from E Revision (July 2015) to F Revision

  • Added clarity to the PIN Function table descriptionsGo
  • Added clarification in Recommended Operating Conditions that GND = PGNDGo
  • Changed (6)maximum VBAT_SAFING to 36 V in the Recommended Operating Conditions table for parameter 1.3a to be consistent with VBATPGo
  • Added VBAT_SAFING input supply voltage range for normal operation RECOMMENDED OPERATING CONDITIONS tableGo
  • Added clarification in statement for the ELECTRICAL CHARACTERISTICS table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating rangeGo
  • Changed description of parameter from Test Condition column to a footnote on the parameter in Electrical Characteristics table for parameters 1.2, 1.7, 2.1, 2.13, 3.1, 3.2, 3.13, 4.2, 5.1, 5.2, 5.3, 5.13, 6.4, 6.5, 6.7, 6.22, 6.23 Go
  • Added clarification on direct loading of VDD6 in the IVDD6 Electrical Characteristics tableGo
  • Changed the Test Condition column to parameter description the ELECTRICAL CHARACTERISTICS table for 2.2, 3.1, 3.2, 5.1, 5.3a, 5.4, 9.3Go
  • Deleted test condition from TJ the Electrical Characteristics table for 5.5 because it is same as overall electrical characteristics table Go
  • Changed Test Condition for input to sensor supply to VSIN from VBATP in the Electrical Characteristics for parameters 5.6, 5.7, 5.8Go
  • Changed the description for indication of VBATP_UV (6.1, 6.2) in the ELECTRICAL CHARACTERISTICS table. Go
  • Added the condition of VBATP = VBAT_SAFING to 6.1, 6.2, 6.3, 6.4, 6.5, 6.8, 6.9, 6.10, 6.11, 6.12, 6.13, 6.14, 6.15, 6.16, 6.17 in the ELECTRICAL CHARACTERISTICS table. Go
  • Added the condition of VBATP = VBAT_SAFING = 12 V to 7.1, 7.2, 7.3, 7.4, 7.7 and 7.8 the ELECTRICAL CHARACTERISTICS tableGo
  • Changed test condition for the I_IGN parameter (7.4) to 36 V, added clarification that VBATP = VBAT_SAFING = 36 V in the ELECTRICAL CHARACTERISTICS table Go
  • Changed test condition for the I_CANWU parameter (7.7) to 36 V, added clarification that VBATP = VBAT_SAFING = 36 V in the ELECTRICAL CHARACTERISTICS table Go
  • Added clarification for Cpump and Cstore connections in the Charge Pump section of the ELECTRICAL CHARACTERISTICS tableGo
  • Changed the Test Condition for NRES output low (paramater 9.1) level from 5mA to 2mA in the ELECTRICAL CHARACTERISTICS table Go
  • Added clarification on resistor divider on regulation tolerance of VDD1 in the VDD1 section of the Electrical Characteristics tableGo
  • Added clarification in statement for the Timing Requirements table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating rangeGo
  • Changed description of parameter from Test Condition column to a footnote on the parameter in the Timing Requirements table for parameters 6.7, 11.1 Go
  • Changed to clarify IGNITION and CAN WAKE-UP parameters (7.6 and 7.9) in TIMING REQUIREMENTS tableGo
  • Added clarification in statement for the Switching Characteristics table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating rangeGo
  • Added clarification of resistor divider feedback impact in the VDD1 Linear Regulator sectionGo
  • Changed pin name to VTRACK1 for pin determining tracking or non-tracking mode in VSOUT1 Linear Regulator section describing what occurs after completion of the VDDx ramp-upGo
  • Added note in the Wake-Up section on how to wake up the device for systems that need to power up and down with the power supply and do not need IGN or CANWU.Go
  • Changed the Power-Up and Power-Down Behavior image for clarityGo
  • Changed the VDD6 UV bit to D6 from D7 in the Voltage Monitoring Overview table Go
  • Changed the name for VSOUT1 current-limit to VSOUT1_CL in the Internal Error Signals table Go
  • Changed all references to the sensor supply to VSOUT1 for consistencyGo
  • Changed to clarify ABIST functionality in the Analog Built-In Self-Test (ABIST) sectionGo
  • Changed LBIST coverage in the Logic Built-In Self-Test (LBIST) sectionGo
  • Changed to clarify LBIST functionality in the Logic Built-In Self-Test (LBIST) sectionGo
  • Changed the impact on device behavior for VSOUT1 thermal protect and over current in the Thermal and Over Current Protect ion Overview table Go
  • Changed the name for VSOUT1 current-limit to VSOUT1_CL in the Digital MUX Selection table Go
  • Changed and clarified Watchdog timer text in the Watchdog Timer (WDT) section Go
  • Changed the all references of ERROR/WDTI pin to ERROR/WDI pin for consistencyGo
  • Added clarification on the watchdog fail counter and reset event requirements in the Watchdog Fail Counter, Status, and Fail Event sectionGo
  • Added the Watchdog Sequence section Go
  • Changed and clarified the equations for watchdog WINDOW 1 and WINDOW 2 (tWOW and tWCW) timing Watchdog Sequence section Go
  • Added the MCU to Watchdog Synchronization section Go
  • Added note on TIME_OUT flag not latching during active SPI frame (nCS low) in the Trigger Mode (Default Mode) sectionGo
  • Added clarification of the impact of a bad event on the watchdog sequence in the Trigger Mode Section and updated the images Go
  • Added note on TIME_OUT flag not latching during active SPI frame (nCS low) in the Q&A Mode sectionGo
  • Changed and clarified the watchdog in Q&A mode answer sequence requirements in the Watchdog Q&A Related Definitions sectionGo
  • Changed the Watchdog Sequence in Q&A Mode image in the Watchdog Sequence in Q&A Mode section to update the Answer-3, Answer-2, Answer-1 requirementsGo
  • Added clarification on when the watchdog Markov chain and question counter are re-initialized in the Question (Token) Generation) sectionGo
  • Added for clarification the Device Controller State DiagramGo
  • Changed SAFETY_ERR_STATUS to SAFETY_ERR_STAT so all references to this register are consistentGo
  • Added clarification on using the DIAG_EXIT_MASK bit for software debug to the end of the DIAGNOSTIC STATE sectionGo
  • Added note to explain conditions leading to inadvert setting of SDO ERROR bit in the Device Status Flag Byte Response sectionGo
  • Added clarification on reserved bits (RSV) in the Register Map section Go
  • Changed DEV_STATE to DEV_STAT for Device Status in Register table for consistencyGo
  • Deleted VSOUT1_ILIM in the SAFETY_STAT_1 Register table and made bit D3 a reserved bit (RSV)Go
  • Changed VDD_3_5_SEL description in SAFETY_FUNC_CFG Register tableGo
  • Changed and clarified the WDT_TOKEN_FDBCK Register table Go
  • Changed and clarified the WDT_WIN1_CFG Register table Go
  • Changed and clarified the WDT_WIN2_CFG Register table Go
  • Changed and clarified the WDT_TOKEN_VALUE Register table Go
  • Changed and clarified the WDT_STATUS Register table Go
  • Changed and clarified the WDT_ANSWER Register table Go
  • Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Q&A Mode flowchartGo
  • Added the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Trigger Mode flowchartGo
  • Added clarity for VBAT_SAFING in the Power Supply Recommendations sectionGo

Changes from D Revision (May 2015) to E Revision

  • Changed the maximum UV value for VDD1 from 0.97 to 0.98 in the Voltage Monitoring Overview table. Also updated the VDD output voltage informationGo
  • Changed the MAX value for VDD1_UVN from 0.97 to 0.98 in the Internal Error Signals table. Also updated the Device State When Flag Is Set cells for VDD1_UVN Go
  • Added clarification on the watchdog fail counter and reset event requirements in the Watchdog Enable Function imageGo
  • Added clarification on the watchdog fail counter and reset event requirements in the Device Controller State DiagramGo

Changes from C Revision (March 2015) to D Revision

  • Changed ƒclk_VDD6 POS 1.5 minimum and maximum units from % to kHz for consistency in the ELECTRICAL CHARACTERISTICS table Go
  • Changed MIN value of VDD1SENSE(4.2) from -2% to -1% in the Electrical Characteristics table Go
  • Changed MAX value of VDD1 undervoltage level (6.16) from 0.97 to 0.98 in the Electrical Characteristics table Go
  • Changed description of un-used VDD1 regulator in the VDD1 Linear Regulator sectionGo
  • Added clarification in the NMASK_VDD1_UV_OV description in the DEV_CFG1 Register tableGo

Changes from B Revision (July 2014) to C Revision

  • Changed Applications listed in the Applications SectionGo
  • Deleted the nominal storage temperature value of 27°C Go
  • Changed the Handling Ratings to ESD Ratings and moved Tstg into the Absolute Maximum Ratings table Go
  • Added clarification notes on output capacitance and ESR for VDD6 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added the Typical Characteristics sectionGo
  • Added clarification of ESR needed on VDD6 output capacitance in the Functional Block DiagramGo
  • Added clarification on effective output capacitance and ESR in theVDD6 Buck Switch Mode Power Supply section Go
  • Added clarification on the IGN and CANWU pins with respect to transients Wake-Up sectionGo
  • Added start-up delay to VCP in the Power-Up and Power-Down BehaviorGo
  • Added SPI Interface Note on use of the SPI while DIAG_OUT MUX is enabled in the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added clarification on the watchdog fail counter and reset event requirements in the WDT Fail Counter, WDT Status, and WDT Fail Event sectionGo
  • Changed the RT bits from 4:0 to 6:0 in the TWCW calculation in the WDTI Configuration With an External Trigger Input (Default Mode) sectionGo
  • Deleted the RT bits from 4:0 to 6:0 in the TWCW calculation in the Watchdog Token-Response Sequence Run section and changed the second calculation from TWOW to TWCWGo
  • Changed WDT_ANSW_CNT answer order in Set of 4-Bit WD Token Values and Corresponding 8-Bit Responses table. Go
  • Changed 4-bit watchdog answer conter to 2-bit watchdog answer counter (WDT_ANSW_CNT) in Watchdog Token-Response Sequence Run and WDT_STATUS Register Updates section . Go
  • Deleted logic BIST activated by MCU in SAFE state in the MCU Error Signal Monitor (MCU ESM)Go
  • Deleted permanently text for the CRC check in the Device Configuration Register Protection section Go
  • Changed CRC check to return to step one for continuous check in the Device Configuration Register Protection sectionGo
  • Added clarification on the watchdog fail counter and reset event requirement in the Reset and Enable Circuit imageGo
  • Added or POST_RUN_RST = 1 & IGN_PWRL = 1 & re-cranking on IGN toGlobal RESET Conditions text bubble of the Device Controller State Diagram image Go
  • Added clarification on watchdog fail counter text to the watchdog reset sub-bullet in the RESET STATE listGo
  • Changed status bit STAT[1] function in Device Status Flag Byte Response tableGo
  • Changed data for SW_LOCK and SW_UNLOCK commands, which were reversed in the SPI Command TableGo
  • Added clarification for watchdog failure in the SAFETY_STAT_2 Register tableGo
  • Added clarification for watchdog failure in the SAFETY_STAT_4 Register tableGo
  • Added ERROR/WDI text to D[5] cleared to description in the SAFETY_ERR_STAT Register tableGo
  • Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register table Go
  • Changed the calculation in the WDT_WIN1_CFG Register table Go
  • Changed the calculation in the WDT_WIN2_CFG Register table Go
  • Added the Typical Application sectionGo
  • Clarified ESR needed on VDD6 output capacitance in the Typical Application DiagramGo
  • Added the System Examples sectionGo
  • Added the Layout sectionGo

Changes from A Revision (December 2013) to B Revision

  • Deleted the phrase safety critical from the document. Go
  • Added device name to document titleGo
  • Added the following to the document: Device Information table, Power Supply Recommendations section, Layout section,Device and Documentation Support, and Mechanical, Packaging, and Orderable Information section Go
  • Changed the pin type for the VDD3/5 pin from I to PWRGo
  • Changed the max value for the Charge-pump voltages from 50 to 52 V in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Added the Handling Ratings table, which now contains the storage temperature and ESD ratings Go
  • Added added with respect to the GND pin to the condition statement in the RECOMMENDED OPERATING CONDITIONSGo
  • Moved operating ambient temperature range from the Absolute Maximum Ratings table to the Recommended Operating Conditions tableGo
  • Changed changed no undervoltage to no NRES event and added VSOUT to the input supply voltage range on VBATP specification in the Recommended Operating ConditionsGo
  • Deleted Thermal Information table notes: all of these notes are included in the IC Package Thermal Metrics application report that is listed in the new table note.Go
  • Added the power dissipation image and notes after the Thermal Information table Go
  • Changed condition statement for the ELECTRICAL CHARACTERISTICS table by removing 125°C from the TA temperature range and changingTJ to the maximum operating junction temperature. Removed VBATP range and added reference to R1.2Go
  • Deleted letter A from beginning of POS number in the VDD6-BUCK With Internal FET and VDD1 – LDO With External FET sections of the Electrical Characteristics and Timing Requirements table Go
  • Changed the parameter name of IVDD6 from output voltage to output current in the Electrical Characteristics tableGo
  • Added the test condition to the dVDD5/dt parameter in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed the typ value from 3.35 to 3.3 and 5 for the VDD3/5 output voltage parameter in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed the unit from † to V for the 3.3, VDD3/5 output voltage dynamic parameter in the Electrical Characteristics tableGo
  • Changed the parameter of 3.8 in the Electrical Characteristics table from VDD5 to VDD6Go
  • Changed the parameter of A4.11 in the Electrical Characteristics table from VBATP to VDD6Go
  • Changed MVVSOUT1 min and max values from –35 and 35 to –25 and 25 in the Electrical Characteristics tableGo
  • Changed the max value for temperature range listed in the VdrS1 parameter test condition from 165 to 150 in the Electrical Characteristics table Go
  • Changed the MIN and MAX values of the LdRegVSOUT1 parameter from –25 and 25 to –35 and 35 in the Electrical Characteristics table Go
  • Changed the typical value for the VDD3/5_OV 5-V hysteresis setting from 400 to 140 in the Electrical Characteristics tableGo
  • Added DC condition note to the VSOUT1_UV and VSOUT1_OV parameters in the Electrical Characteristics table Go
  • Changed max value for the Rdson_ENDRV_NRES (9.2a) parameter from 86 to 40 in the Electrical characteristics table Go
  • Deleted note reference for the RRSTEXT parameter (9.3) in the Electrical Characteristics tableGo
  • Changed min value from 300 to 350 for the VENDRV_NRES_TH (9.5) parameter in the ELECTRICAL CHARACTERISTICS table Go
  • Added note reference and test condition to the VDIGIN_HIGH parameter (10.1) in the ELECTRICAL CHARACTERISTICS table Go
  • Moved timing and switching characteristics out of the Electrical Characteristics table and into a Timing Requirements and Switching Requirements table (respectively). Also moved the capacitance at CSDO note to the Timing Requirements and Switching Requirements tablesGo
  • Changed the TYP value to the MAX value of the SPI clock frequency parameter for the VDDIO = 5 V test condition in the Electrical Characteristics table Go
  • Added image reference to timing and switching requirement parameters Go
  • Changed max value of ttri (13.11) from 25 to 53.3 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added the Overview section to the Detailed Description sectionGo
  • Moved block diagram into the Detailed Description section and updated block colorsGo
  • Changed the OV max value for VDD3/5 (3.3 V) from 3.63 to 3.6 in the Voltage Monitoring Overview table Go
  • Added nMASK comments to the UV and OV impact on device behavior for VDD1 in the Voltage Monitoring Overview tableGo
  • Moved the Internal Error Signals table to after the Voltage Monitoring Overview table in the Detailed Description section Go
  • Changed the TYP value for the AVDD_UVN signal from 3.81 to 3.6 in the Internal Error Signals table. Also changed the device state from Not changed for NRES and ENDRV to LOW, and for State to STANDBY Go
  • Changed the TYP value for the VCP12_UVN signal from 7.32 to 7.43 in the Internal Error Signals table Go
  • Changed the TYP value for the VCP12_OV signal from 14 to 14.2 in the Internal Error Signals table Go
  • Changed the typ value for VCP_OV from 20 to 21 in the Internal Error Signals table Go
  • Changed NUV on signal names to UVN throughout Go
  • Changed the MIN value for the LOCLK signal from 0.740.7452 to 0.742 in the Internal Error Signals table Go
  • Changed the VBATP_OV MIN and MAX values from 29 to 34.7 and 32 to 36.7 (respectively) in the Internal Error Signals table Go
  • Changed the device state of the VDD3_5_OT bit from STANDBY to include change Go
  • Changed the max values for VDD5_CL and VDD3_5_CL from 600 to 650 in the Internal Error Signals table Go
  • Added the DVDD_UV signal to the Internal Error Signals table Go
  • Changed Go
  • Deleted Watchdog function configuration from the post-BIST-reset initialization list in the Logic Built-In Self-Test (LBIST) sectionGo
  • Changed VCP voltage range from 0.8 to 5.5 to 0.6 to 4 Go
  • Replaced the VSFB1 sensor-supply feedback voltage row wit the VSOUT1 sensor-supply voltage row in the Analog MUX Selection TableGo
  • Changed VSFB1 divide ratio from 4 ± 0.5% to 1 in the Analog MUX Selection table. Also changed the Voltage Range from 1.226 V to 5 V ±2% to 2.5 V to 5 V Go
  • Changed the Voltage Range / Accuracy value for both MAIN_BG and VMON_BG from 1.226 to 2.5 V in the Analog MUX Selection tableGo
  • Changed the name bit that must be configured for DIGITAL MUX mode from DIAG_MUX to MUX_CFG in the Digital MUX (DMUX) section Go
  • Deleted Bits INT_CON[2:0] in DIAG_CFG_CTRL register must be set to 111 list item from the SDO diagnostic check sequence in the MUX interconnect check sectionGo
  • Changed the RT bits from 4:0 to 6:0 in the TWCW calculation in the WDTI Configuration With an External Trigger Input (Default Mode) sectionGo
  • Deleted the CLOSE window note from the Possible Cases for Bad Watchdog Event image and updated the imageGo
  • Added + 1 to the duration time program calculations in the Watchdog Token-Response Sequence Run section and changed the second calculation from TWOW to TWCWGo
  • Changed the filter time for the ERROR/WDI deglitch from 15-s to 15-µs in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Changed the low-pulse duration increment from 15-s to 15-µs in the PWM Mode sectionGo
  • Changed the Reset and Enable Circuit figure to reflect overtemperature behavior.Go
  • Added _UV to the NMASK_VDD1_OV name in the Reset and Enable Circuit image Go
  • Added _UV to the NMASK_VDD1_OV name in DIAGNOSTIC and ACTIVE state text box of the Device Controller State Diagram image Go
  • Deleted WDT failure text from the first list item in the SAFE State section Go
  • Moved all of the registers into one Register Map section Go
  • Changed D0 from 1 to 0 in the DEV_REV Register tableGo
  • Changed D1 and D0 from 0 to X in the DEV_STATE Register tableGo
  • Changed the deglitched minimum time from 7.7 to 7.5 for the IGN bit description in the DEV_STATE register Go
  • Changed D7 from RSV and 1 to VDD_3_5_SEL and X in the DEV_CFG1 Register tableGo
  • Changed D6 from nMASK_VDD_UV and 1 to nMASK_VDD_UV_OV and 0 in the DEV_CFG1 Register tableGo
  • Changed the default value of the NMASK_VDD1_UV_OV bit from 1 to 0 and the VDD1 bit value from 0 to 1 in the DEV_CFG1 RegisterGo
  • Changed bit D5 name from MASK_VBAT_OV to MASK_VBATP_OV in the DEV_CFG2 Register tableGo
  • Changed the D[7] description when EN_VDD3/5_OT is set to '0' by removing the SAFETY_STAT_REG1, VDD6 and re-enable text in the DEV_CFG2 Register table. Also changed from when set to '0' to when set to '1' Go
  • Changed VDD6, clearing, and re-enabling text from the D[7] description when EN_VDD3/5_OT is set to '1' and changed to when set to ''' in the DEV_CFG2 Register tableGo
  • Changed D[3:0] description in the DEV_CFG2 Register table from bits are not read/writable to bits are read/writableGo
  • Deleted after SPI read access from the clear to 0 description of each bit in the VMON_STAT_1 RegisterGo
  • Deleted after SPI read access from the clear to 0 description of each bit in the VMON_STAT_2 RegisterGo
  • Deleted after SPI read access from the clear to 0 description of each bit in the SAFETY_STAT_1 RegisterGo
  • Deleted after SPI read access from the clear to 0 description of each bit in the SAFETY_STAT_2 RegisterGo
  • Added description to bit D[4] when set to one 1 when the device is the DIAGNOSTIC state Go
  • Changed the name of bit D5 in the SAFETY_STAT_3 register from NRES_IN to NRES_ERRGo
  • Changed the D[5] NRES_IN, Reset input status, register description to NRES_ERR, Reset input error and change first description for setting this bit to 1Go
  • Updated cleared to 0 description of the LBIST_ERR bit in the SAFETY_STAT_3 register Go
  • Added DIAGNOSTIC state description for setting bit D[3] and D[2] to 1 Go
  • Changed SPI read access to internal NPOR from the LOCLK bit description in the SAFETY_STAT_4 RegisterGo
  • Changed bit D7 and bit D6 from 1 to 0 in the SAFETY_ERR_CFG Register tableGo
  • Changed the SAFETY_STAT4 register bit from D4 to D5 in the ABIST_EN[1:0] descriptions in the SAFETY_BIST_CTRL Register table Go
  • Changed names of protected registers in the CRG_CRC_EN bit description in the SAFETY_CHECK_CTRL RegisterGo
  • Changed monitored to not monitored in the NO_ERROR bit description for setting this bit to 1 in the SAFETY_CHECK_CTRL Register Go
  • Changed CTRL to CFG in the read and write commands of the SAFETY_FUNC_CFG RegisterGo
  • Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register tableGo
  • Changed D4 from 1 to 0 in the SAFETY_FUNC_CFG Register tableGo
  • Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register tableGo
  • Updated the WD_RST_EN bit description for setting this bit to 0 in the SAFETY_FUNC_CFG Register Go
  • Changed 15 seconds to 15 µs in the SAFETY_ERR_PWM_H Register table descriptionGo
  • Changed the time reference amount from 15 s to 15 µs in the PWML[7:0] bit description for when ERR_CFG is set to 0 in the SAFETY_ERR_PWM_L Register Go
  • Changed 5 seconds to 5 µs in the SAFETY_ERR_PWM_H Register table descriptionGo
  • Deleted Note: With configuration 001 setting for INT_CON[2:0] bits text from the SPI_SDO description in the DIAG_CFG_CTRL Register. Also changed the 111 description of the INT_CON[2:0}] from controlling the state of the SPI_SDO output buffer to Not applicableGo
  • Included bit 2 to all WDT_FAIL_CNT bit references Go
  • Changed command for the WDT_ANSWER Register from Read to WriteGo
  • Changed the default setting of VSOUT1_EN from 1 to in the SENS_CTRL Register tabelGo
  • Changed Moved the Application Information section into the Application and Implementation section and added product folder referencesGo

Changes from * Revision (May 2012) to A Revision

  • Changed current limit for 6-V pre-regulator from 1.5 A to 1.3 A in the FEATURES listGo
  • Added current limit to the 5-V (CAN) bullet in the FEATURES list Go
  • Added current limit to the 3.3-V or 5-V MCU I/O Voltage bullet in the FEATURES list Go
  • Deleted reverse battery protection bullet from the FEATURES listGo
  • Changed current limit from 300 mA to 100 mA in the sensor supply bullet in the FEATURES list Go
  • Deleted wake-up and enable circuit bullets from the FEATURES listGo
  • Added Independent to voltage monitoring bullet in the FEATURES listGo
  • Added Independent Bandgap Reference bullet to the FEATURES listGo
  • Added Diagnostic Output Pin bullet to the FEATURES listGo
  • Added Safing-Pin and IGNITION Pin bullets to the FEATURES listGo
  • Changed document status from Product Preview to Production DataGo
  • Added CAN Transceiver sentence to the second paragraph in the DESCRIPTIONGo
  • Changed adjustable core voltage range from 0.8 and 2.6 V to 0.8 and 3.3 V in the DESCRIPTIONGo
  • Added diagnostic output pin and enable output to the list of features listed in the eighth paragraph in the DESCRIPTIONGo
  • Changed to data manual template to include table of contents and section numbersGo
  • Added ADC, VDD6, to Typical Application DiagramGo
  • Changed PGND type from input to ground in PIN FUNCTIONS tableGo
  • Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustmentsGo
  • Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustmentsGo
  • Added Charge-pump overdrive voltage to the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted DMUXO from Logic I/O voltage list (M1.15) in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table Go
  • Changed unit for CDM on corner pins (750) from kV to V in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table Go
  • Deleted VDDIO internal pullup diode note from the RECOMMENDED OPERATING CONDITIONS tableGo
  • Added values to the current consumption parameter in the RECOMMENDED OPERATING CONDITIONS tableGo
  • Changed condition statement for the ELECTRICAL CHARACTERISTICS table by adding TA over junction temperature with up to 150°CGo
  • Added VDD6ripple parameter to the ELECTRICAL CHARACTERISTICS tableGo
  • Added VDD6 output voltage to IVDD6 parameter (A1.2) in the ELECTRICAL CHARACTERISTICS table Go
  • Changed example to Vdropout6 (A1.3) test condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed IVDD6_limit parameter description from current-limit to peak current in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed A1.5 from Fsw_VDD6, switching frequency to ƒclk_VDD6, clock frequency, added note, and deleted test condition from the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Changed test condition for DCVDD6 parameter (A1.6) from VBATP > 7 V to 0 <IVDD6 < 1.3 A in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVDD6 (A1.7) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Global shutdown to Protection of VDD6, shared with VDD3/5 thermal protection. for both TprotVDD6 parametersGo
  • Added Hysteresis parameter, min and max values to TprotVDD5 (2.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from VDD5 switch-off to Protection of VDD5.In case of detected over-temperature, only VDD5 will be switched-off for both TprotVDD5 parametersGo
  • Added VDD3/5 end-value to test condition for the dVDD35/dt parameter (3.11) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVDD3/5 (3.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Global shutdown to Protection of VDD3/5, treated as global thermal shutdown (shutdown for all regulators) for both TprotVDD3/5 parametersGo
  • Added test condition to the dVDD1/dt parameter (A4.14) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added VSOUT1 text to test condition for VSOUT1 parameter (5.1) in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed MVVSOUT1 min and max values from –15 and 15 to –35 and 35 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added min and max values for the Threshold for tracking/non-tracking parameter in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVSOUT1 (5.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from VSOUT1 switch-off to Protection of Sensor Supply. Only VSOUT1 switch-off for both TprotVSOUT1 parametersGo
  • Changed min and max values for VBATP_OVrise parameter from 29.5 and 32.5 to 34.7 and 36.7 (respectively) in the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Deleted VBATP_OVhys (POS 6.6) from the ELECTRICAL CHARACTERISTICS tableGo
  • Changed min and max values for VBATP_OVfall parameter from 29 and 32 to 34.4 and 36.3 (respectively) in the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Added Hysteresis parameter, min and max values to VDD5_UV (6.8) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed max value for VDD5_OV from 5.5 to 5.45 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to VDD5_OV (6.10) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed min value for VDD3/5_UV with test condition of 3.3-V setting (undervoltage) from 2.97 to 3 in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value for VDD3/5_UV with test condition of 5-V setting (undervoltage) from 4.8 to 4.85 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter for 3.3 and 5 V settings, min and max values to VDD3/5_UV (6.12) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed max value for VDD3/5_OV with test condition of 3.3-V setting from 3.63 to 3.6 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter for 3.3 and 5 V settings, min and max values to VDD3/5_OV (6.14) in the ELECTRICAL CHARACTERISTICS table. Go
  • Added Hysteresis parameter, min and max values to VDD1_UV (6.16) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VDD1_SENSE pin to Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) for both VDD1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD1_OV (6.17) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VDD1_SENSE pin to Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) for both VDD1_OV parametersGo
  • Added Hysteresis parameter, min and max values to VSOUT1_UV (6.19) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VSFB1 pin to Sensed on VSFB1 pin Relative thresholds are: for both VSOUT1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VSOUT1_UV (6.20) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VSFB1 pin to Sensed on VSFB1 pin Relative thresholds are: for both VSOUT1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD6_UV (6.22) in the ELECTRICAL CHARACTERISTICS table. Also added test condition for both VDD6_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD6_OV (6.23) in the ELECTRICAL CHARACTERISTICS table. Also added test condition for both VDD6_OV parametersGo
  • Added test condition to the I_IGN parameter in the the ELECTRICAL CHARACTERISTICS table(7.4)Go
  • Changed I_CAN parameter (7.7) to I_CANWU and added test condition to the ELECTRICAL CHARACTERISTICS tableGo
  • Changed I_CAN_rev (7.8) max value from 1 to –1 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added test condition for ICP (8.2) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added min and max values for fCP (8.3) in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted min value of 11 for the Rdson_ENDRV_NRES (9.2a) parameter in the ELECTRICAL CHARACTERISTICS table Go
  • Added input and logic 1 to the VENDRV_NRES_TH parameter (9.5) description in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted max value from 500 to 450 for the VENDRV_NRES_TH (9.5) parameter in the ELECTRICAL CHARACTERISTICS table Go
  • Added note reference and test condition to the VDIGIN_LOW parameter (10.2) in the ELECTRICAL CHARACTERISTICS table Go
  • Added note reference and test condition to the VDIGIN_HYST parameter (10.3) in the ELECTRICAL CHARACTERISTICS table. Also added parameter nameGo
  • Changed 10.4 from empty to the RDIAGOUT_AMUX parameter to the ELECTRICAL CHARACTERISTICS table Go
  • Added pin note to the VDIGOUT_HIGH parameter (10.5) in the ELECTRICAL CHARACTERISTICS table Go
  • Added pin note to the VDIGOUT_LOW parameter (10.6) in the ELECTRICAL CHARACTERISTICS table Go
  • Added min and max values for tRSTEXT(0kΩ) (9.4a) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added tWD_pulse parameter to the ELECTRICAL CHARACTERISTICS tableGo
  • Added for MCU error signal monitor to the tERROR_WDI_deglitch parameter (12.1) in the ELECTRICAL CHARACTERISTICS table Go
  • Changed max value for the tERROR_WDI_deglitch parameter (12.1) from 15.75 to 16.25 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added two test conditions to the fSPI parameter (13.1) and removed the single max value of 8 to replace it with the max value for each condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Added two test conditions to the tSPI parameter (13.2) and removed the single min value of 125 to replace it with the min value for each condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value for tsusi(13.7) to min value in the ELECTRICAL CHARACTERISTICS table. Also changed parameter description from rising edge to falling edge of SCLKGo
  • Changed min value from 250 to 788 for the thlcs parameter (13.10) in the ELECTRICAL CHARACTERISTICS table. Also added NCS high text to parameter descriptionGo
  • Added test condition to the fSysclk parameter (11.1) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added SDO transition from tri-state to td1 parameter (13.6) description in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of td1 from 30 to 53.3 in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of td2 from 30 to 85.7 in the ELECTRICAL CHARACTERISTICS table. parameter description from falling edge to rising edge of SCLKGo
  • Changed ttri parameter (13.11) description from Hi-Z state to tristate in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of ttri (13.11) from 15 to 25 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added td2 to right side of SPI Timing Parameters diagramGo
  • Added the SPI SDO Buffer Source/Sink Current graph after the ELECTRICAL CHARACTERISTICS tableGo
  • Changed block diagramGo
  • Added condition for when the N-channel MOSFET turns on to the second paragraph in the VDD6 Buck Switch Mode Power Supply section Go
  • Deleted clearing out of SAFETY_STAT from re-enable VDD5 paragraph and changed SENS_CTRL bit from 4 to D4 in the VDD5 Linear Regulator sectionGo
  • Added the default VDD1 paragraph to the end of the VDD1 Linear Regulator sectionGo
  • Added sentence to the first paragraph in the VSOUT1 Linear Regulator section describing what occurs after completion of the VDDx ramp-upGo
  • Changed tracking offset from ±15 to ±35 in the VSOUT1 Linear Regulator sectionGo
  • Added SPI command setting to the seventh paragraph in the VSOUT1 Linear Regulator sectionGo
  • Added DIAGNOSTIC state text to the Wake-Up sectionGo
  • Changed second paragraph in the Wake-Up section: changed edge-sensitive to level-sensitive and pulse duration to deglitch time.Go
  • Added during a power-up event to the Reset Extension section and removed VDD1 from the descriptionGo
  • Deleted open-connect and RESET state sentence from the last paragraph in the Reset Extension sectionGo
  • Changed Power-Up and Power-Down Behavior image in the Power-Up and Power-Down Behavior sectionGo
  • Added notes to theIGN Power Latch and POST-RUN Reset image in the Power-Up and Power-Down Behavior sectionGo
  • Deleted reset driver from ENDRV bullet in the Safety Functions and Diagnostics Overview section Go
  • Added the Voltage Monitoring Overview table and table reference to the Voltage Monitor (VMON) sectionGo
  • Added the Internal Error Signals tableGo
  • Deleted loss-of-power note and cleared-latched bullet from the clock failure list in the Loss-of-Clock Monitor (LCMON) sectionGo
  • Added SPI register bit to the latched bullet in the clock failure list in the Loss-of-Clock Monitor (LCMON) sectionGo
  • Added ABIST case paragraphs following the Analog BIST Run States imageGo
  • Moved Logic Built-In Self-Test (LBIST) section from after DMUX tables and added initialized registers listGo
  • Deleted VDD5 and VSOUT1 supplies from first paragraph of the Junction Temperature Monitoring and Current Limiting section Go
  • Added VSOUT1 supplies paragraph to the Junction Temperature Monitoring and Current Limiting sectionGo
  • Added Go
  • Deleted STANDBY State text from the Junction Temperature Monitoring and Current Limiting section and changed to regulated supplies. Also added ENDRV pinGo
  • Changed third paragraph of the Junction Temperature Monitoring and Current Limiting section to include NRES asserted low and VDD5 reenable Go
  • Added Thermal and Overcurrent Protect Overview table and table reference to the Junction Temperature Monitoring and Current Limiting sectionGo
  • Added analog and digital signals and notes to the Diagnostic Output Pin DIAG_OUT image in the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added added disabled state description for the DIAG_OUT pin in the last paragraph of the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added accuracy and corresponding table note to the voltage range column in the Analog MUX Selection tableGo
  • Added ± percentage to the divide ratio values (except for MAIN_BG and VMON_BG) the Analog MUX Selection tableGo
  • Changed the DIAG_MUX_SEL column and header in the Analog MUX Selection tableGo
  • Added the max output resistance column to the Analog MUX Selection tableGo
  • Changed VSFB1 divide ratio from 1 to 4 in the Analog MUX Selection Table Go
  • Added the voltage/signal name for signal number A.7 from BG1 to MAIN_BG in the Analog MUX Selection tableGo
  • Added additional text and note to further explain the Analog MUX Selection Table Go
  • Added second paragraph to the Digital MUX (DMUX) sectionGo
  • Added diagnostic check text, Diagnostic MUX Output state (by MUX_OUT bit), and MUX interconnect check section after DMUX tablesGo
  • Changed the Watchdog Enable Function image in the WDT Fail Counter, WDT Status, and WDT Fail Event sectionGo
  • Added watchdog fail counter text after the Watchdog Status for Fail Counter Value Range tableGo
  • Changed trigger events paragraph (third) in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added SPI register names and DIAGNOSTIC state to the open and close window programming sentence in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added the WDTI window sequencing and SPI SW_LOCK paragraphs in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added the WDTI rising edge paragraph in the WDTI Configuration with External Trigger Input (Default Mode) section and added tWD_pulse filter time paragraphGo
  • Added image to the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added image to the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Deleted ASIC reference in the first paragraph of the Watchdog Question /and Answer Configuration Through SPI sectionGo
  • Added starts a new watchdog token-response sequence run to the no-response event description in paragraph four of the Watchdog Question /and Answer Configuration Through SPI sectionGo
  • Added 4-bit word bullet to the Watchdog Token Request definition list in the Watchdog-Timer-Related SPI Event Definitions sectionGo
  • Added 32-bit word bullet to the Watchdog Token Timer Request definition list in the Watchdog-Timer-Related SPI Event Definitions sectionGo
  • Added Watchdog Token-Response Sequence Run section to replace the Watchdog Timer Configuration for Question and Answer Configuration sectionGo
  • Changed the WDT Token and Response Sequence Run image in the Watchdog Token-Response Sequence Run sectionGo
  • Added the 4-bit question paragraph to the Watchdog Token Value Generation (or Watchdog Question Generation) sectionGo
  • Added the Watchdog TOKEN Generation image and following text in the Watchdog Timer Configuration for Question and Answer Configuration sectionGo
  • Added Answer Comparison and Reference Answer sectionGo
  • Changed WDT answer column header names - switched response 0 and response 3, switched response 2 and response 1 in the Set of 4-Bit WD Token Values and Corresponding 8-Bit Responses table. Added token registerDevice Configuration Register Protection name and value to token column.Go
  • Added Watchdog Token-Response Sequence Run and WDT_STATUS Register Updates sectionGo
  • Added activation and deactivation paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added DIAGNOSTIC and ACTIVE state paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added deglitched and synchronized paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added ERROR/WDI pin implementation text in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added the first paragraph in the PWM Mode section and added the detect and no detect statementsGo
  • Added monitoring lists to the PWM Mode sectionGo
  • Changed register setting text for the ERROR_PIN_FAIL bit from error-pin signaling failure to system clock detection to the PWM Mode sectionGo
  • Added CFG_CRC_ERR flag text to the Device Configuration Register Protection section Go
  • Changed CRC-8 polynomial from X8 + X7 + X6 + X4 + X2 + 1 to X8 + X2 + X1 + 1 in the Device Configuration Register Protection sectionGo
  • Added 64-bit string text and protected registers list in the Device Configuration Register Protection sectionGo
  • Added CRC Bus Structure table in the Device Configuration Register Protection sectionGo
  • Added CRC calculation text, image, and table in the Device Configuration Register Protection sectionGo
  • Added EEPROM CRC check and list of steps in the Device Configuration Register Protection sectionGo
  • Changed the Reset and Enable Circuit image in the Enable and Reset Driver Circuit sectionGo
  • Added ENDRV pulled low paragraph to the Enable and Reset Driver Circuit sectionGo
  • Changed timing-response diagram description from RESET condition to any VDDx UV or OV condition in the Enable and Reset Driver Circuit sectionGo
  • Added RESET condition image in the Enable and Reset Driver Circuit section and replaced it with the any VDDx UV or OV condition imageGo
  • Changed Device Controller State Diagram imageGo
  • Added Internal NPOR (power-on reset) bullet item in the STANDBY STATE sectionGo
  • Changed IGN and CANWU driven low bullet item to deglitched IGN, IGN_PWRL, and CANWU_L with values in the STANDBY STATE sectionGo
  • Added device error count text to the SAFE state bullet in the RESET STATE listGo
  • Deleted the ACTIVE state bullet in the RESET STATE listGo
  • Added VDD5 sub-bullet in the RESET STATE listGo
  • Added watchdog fail counter text to the watchdog reset sub-bullet in the RESET STATE listGo
  • Added ramping up sub-bullet to the first item in the RESET STATE listGo
  • Added RESET State transition paragraph to the RESET STATE listGo
  • Added NRES pulled up to the Enters RESET state bullet in the DIAGNOSTIC STATE listGo
  • Added VSOUT1, watchdog and ERROR/WDI, watchdog failure counter, and ENDRV pin bullets in the DIAGNOSTIC STATE listGo
  • Added DIAG_EXIT_MASK and DIAG_EXIT text to the end of the DIAGNOSTIC STATE listGo
  • Changed two bullets in the ACTIVE STATE list and added three additional bulletsGo
  • Added uncontrolled transition sub-bullet to the enters DIAGNOSTIC state bullet in the SAFE STATE listGo
  • Added ACTIVE state read-back error, stays in Safe state, NRES, and VDDx bullets in the SAFE STATE listGo
  • Added STATE TRANSITION PRIORITIES sectionGo
  • Deleted Enters from RESET, DIAGNOSTIC, or ACTIVE state after ABIST or LBIST failure bullet from the SPI 4-pin list in the SPI Interface sectionGo
  • Changed speed from 10 to 6 Mbit/s in the SPI Interface sectionGo
  • Added minimum time sentence to paragraph after the SPI Command Transfer Phase table Go
  • Deleted paragraph describing the possibility of mixing two access modes in the SPI Data-Transfer Phase sectionGo
  • Added minimum time sentence to paragraph after the SPI Data-Transfer Phase tableGo
  • Added status bit paragraph and note after the Device Status Flag Byte Response tableGo
  • Added 8-bit hex column to the SPI Command TableGo
  • Changed D5 from 0 to 1 in the DEV_REV Register tableGo
  • Changed D0 from 0 to 1 in the DEV_REV Register tableGo
  • Changed D0 from 0 to 1 in the DEV_ID Register tableGo
  • Changed reset value text to D[1] and D[0] descriptions in the DEV_STATE Register tableGo
  • Changed D6 from MASK_VDD_OV and 1 to nMASK_VDD_UV_OV and 0 in the DEV_CFG1 Register tableGo
  • Added ground and no ground to the SEL_VDD3/5 description for both 5 V and 3.3 V in the DEV_CFG1 Register tableGo
  • Added value in RESET State text in the DEV_CFG1 Register tableGo
  • Added READ-ONLY the DEV_CFG1 Register tableGo
  • Added after first start-up text to D[6] if VDD1 text in the DEV_CFG1 Register tableGo
  • Switched the names of D5 and D4 in DEV_CFG2 Register tableGo
  • Changed EN_VDD3/5_OT description by removing extra text after set to 1 and adding two more bullets in the DEV_CFG2 Register tableGo
  • Changed read/writable text for D[3:0] in the DEV_CFG2 Register tableGo
  • Changed AVDD_VMON_ERR description from error status to power-good status in the VMON_STAT_1 Register tableGo
  • Changed set to 1 text of D[1] in the VMON_STAT_1 Register table from when error is detected to when voltage monitor < main band gap Go
  • Changed set to 1 text of D[0] in the VMON_STAT_1 Register table froGo
  • Changed m when error is detected to when voltage monitor > main band gap Go
  • Changed name of D6 from VDD3_ILIM to VDD3_5_ILIM in the SAFETY_STAT_1 Register tableGo
  • Added note to D[7] description in the SAFETY_STAT_1 Register tableGo
  • Added EEPROM bullet to D[5] description in the SAFETY_STAT_2 Register tableGo
  • Added DIAGNOSTIC and ACTIVE State text to D[2:0] default bullet in the SAFETY_STAT_2 Register tableGo
  • Added cleared to text to the D[5] description in the SAFETY_STAT_3 Register tableGo
  • Changed D7 and D6 from 1 to 0 in the SAFETY_STAT_4 Register tableGo
  • Changed name of D0 from TRIM_ERR to TRIM_ERR_VMON in the SAFETY_STAT_4 Register tableGo
  • Added cleared to bullet and note to D[7:6] description in the SAFETY_STAT_4 Register tableGo
  • Changed set to text to include error-signal monitoring in the D[3] description in the SAFETY_STAT_4 Register tableGo
  • Added ERROR_PIN_FAIL text to D[3] cleared description in the SAFETY_STAT_4 Register tableGo
  • Added Watchdog Fail Counter text to the D[2] set to and cleared to descriptions in the SAFETY_STAT_4 Register tableGo
  • Deleted SPI read access from D[1]cleared to description in the SAFETY_STAT_4 Register table Go
  • Changed SPI read access to NPOR in the D[0]cleared to description in the SAFETY_STAT_4 Register table Go
  • Changed D4 from 1 to 0 and D1 and D0 from 0 to 1 in the SAFETY_STAT_5 Register tableGo
  • Changed threshold from max to min for the 0000 setting description in the SAFETY_ERR_CFG Register tableGo
  • Changed D7 and D6 from 1 to 0 in the SAFETY_BIST_CTRL Register tableGo
  • Changed D3 from LOCLK_EN to RSV in the SAFETY_BIST_CTRL Register tableGo
  • Added ACTIVE state bullet to D[7:6] description in the SAFETY_BIST_CTRL Register tableGo
  • Added DIAGNOSTIC and ACTIVE states to D[5] description in the SAFETY_BIST_CTRL Register tableGo
  • Changed D4 from NO_WRST to RSV in the SAFETY_CHECK_CTRL Register tableGo
  • Added DEV_CFG2 and DEV_CFG1 to D[7] list of protected registers in the SAFETY_CHECK_CTRL Register tableGo
  • Added device state, ENDRV and NRES to D[6] description in the SAFETY_CHECK_CTRL Register tableGo
  • Changed D[3] from not read/writable to read/writable in the SAFETY_CHECK_CTRL Register tableGo
  • Added ERROR_PIN_FAIL sub-bullet to D[2] descriptionin the SAFETY_CHECK_CTRL Register table Go
  • Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register tableGo
  • Changed D2 from RSV to DIS_NRES_MON in the SAFETY_FUNC_CFG Register tableGo
  • Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register tableGo
  • Added SAFE state-time sub-bullet to the D[7] description in the SAFETY_FUNC_CFG Register tableGo
  • Changed D[6] description from error-pin to Error-Signal Monitor in the SAFETY_FUNC_CFG Register tableGo
  • Deleted watchdog pin from the D[6] description in the SAFETY_FUNC_CFG Register tableGo
  • Added note text to the D[4] description in the SAFETY_FUNC_CFG Register tableGo
  • Added STANDBY state text to the D[4] description in the SAFETY_FUNC_CFG Register tableGo
  • Deleted enabling/disabling the watchdog bullet from the D[3] description in the SAFETY_FUNC_CFG Register tableGo
  • Added bullets to the D[2] description in the SAFETY_FUNC_CFG Register tableGo
  • Changed D[1] from not read/writable to read/writable in the SAFETY_FUNC_CFG Register tableGo
  • Added READ-ONLY bullet, RESET STATE sub-bullet, and connected and not-connected text to the D[0] description in the SAFETY_FUNC_CFG Register tableGo
  • Added ERROR/WDI and SAFE state text to the D[5] set to description in the SAFETY_ERR_STAT Register tableGo
  • Added WD_RST_EN text to D[4] set to description in the SAFETY_ERR_STAT Register tableGo
  • Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register tableGo
  • Added equation and oscillator text to the SAFETY_ERR_PWM_H Register table descriptionGo
  • Changed D4, D2, and D0 from 0 to 1 in the SAFETY_ERR_PWM_L Register descriptionGo
  • Added equations and oscillator text to the SAFETY_ERR_PWM_H Register table descriptionGo
  • Changed D4 from 1 to 0 in theSAFETY_PWD_THR_CFG Register tableGo
  • Changed _THR to PWD names for D3:D0 in theSAFETY_PWD_THR_CFG Register tableGo
  • Changed D7, D5, and D3 from 1 to 0 in the SAFETY_CFG_CRC Register tableGo
  • Changed D4 from 0 to 1 in the SAFETY_CFG_CRC Register tableGo
  • Changed D[7] description from high-impedance to tri-stated in the DIAG_CFG_CTRL Register tableGo
  • Added SDO diagnostics from D[1:0] description to the D[6] description in the DIAG_CFG_CTRL Register tableGo
  • Changed D2 from 1 to 0 in the WDT_TOKEN_FDBCK Register table Go
  • Added bullets to the D[7:4] description in the WDT_TOKEN_FDBCK Register table Go
  • Added new TOKEN seed bullet and sub-bullets to the D[3:0] description in the WDT_TOKEN_FDBCK Register table Go
  • Changed D6:D0 from 0 to 1 in the WDT_WIN1_CFG Register table Go
  • Changed D4:D3 from 0 to 1 in the WDT_WIN2_CFG Register tableGo
  • Changed D7 from 0 to 1 in the WDT_TOKEN_VALUE Register tableGo
  • Changed MCU sub-bullet from D[7] description to replace Q&A sub-bullet in the D[3:0] description of the WDT_TOKEN_VALUE Register tableGo
  • Changed D7:D6 from 0 to 1 in the WDT_STATUS Register tableGo
  • Changed D7:DF from RSV to WD_WRONG_CFG in the WDT_STATUS Register tableGo
  • Changed set to text of the D[5] description in the WDT_STATUS Register table Go
  • Changed D[4] note from recommendation to clear bit to remains set to 1 in the SENS_CTRL Register table Go
  • Changed Typical Application Diagram imageGo

Changes from * Revision (July 2016) to A Revision

  • Changed current limit for 6-V pre-regulator from 1.5 A to 1.3 A in the FEATURES listGo
  • Added current limit to the 5-V (CAN) bullet in the FEATURES list Go
  • Added current limit to the 3.3-V or 5-V MCU I/O Voltage bullet in the FEATURES list Go
  • Deleted reverse battery protection bullet from the FEATURES listGo
  • Changed current limit from 300 mA to 100 mA in the sensor supply bullet in the FEATURES list Go
  • Deleted wake-up and enable circuit bullets from the FEATURES listGo
  • Added Independent to voltage monitoring bullet in the FEATURES listGo
  • Added Independent Bandgap Reference bullet to the FEATURES listGo
  • Added Diagnostic Output Pin bullet to the FEATURES listGo
  • Added Safing-Pin and IGNITION Pin bullets to the FEATURES listGo
  • Changed document status from Product Preview to Production DataGo
  • Added CAN Transceiver sentence to the second paragraph in the DESCRIPTIONGo
  • Changed adjustable core voltage range from 0.8 and 2.6 V to 0.8 and 3.3 V in the DESCRIPTIONGo
  • Added diagnostic output pin and enable output to the list of features listed in the eighth paragraph in the DESCRIPTIONGo
  • Changed to data manual template to include table of contents and section numbersGo
  • Added ADC, VDD6, to Typical Application DiagramGo
  • Changed PGND type from input to ground in PIN FUNCTIONS tableGo
  • Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustmentsGo
  • Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustmentsGo
  • Added Charge-pump overdrive voltage to the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted DMUXO from Logic I/O voltage list (M1.15) in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table Go
  • Changed unit for CDM on corner pins (750) from kV to V in the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table Go
  • Deleted VDDIO internal pullup diode note from the RECOMMENDED OPERATING CONDITIONS tableGo
  • Added values to the current consumption parameter in the RECOMMENDED OPERATING CONDITIONS tableGo
  • Changed condition statement for the ELECTRICAL CHARACTERISTICS table by adding TA over junction temperature with up to 150°CGo
  • Added VDD6ripple parameter to the ELECTRICAL CHARACTERISTICS tableGo
  • Added VDD6 output voltage to IVDD6 parameter (A1.2) in the ELECTRICAL CHARACTERISTICS table Go
  • Changed example to Vdropout6 (A1.3) test condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed IVDD6_limit parameter description from current-limit to peak current in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed A1.5 from Fsw_VDD6, switching frequency to ƒclk_VDD6, clock frequency, added note, and deleted test condition from the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Changed test condition for DCVDD6 parameter (A1.6) from VBATP > 7 V to 0 <IVDD6 < 1.3 A in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVDD6 (A1.7) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Global shutdown to Protection of VDD6, shared with VDD3/5 thermal protection. for both TprotVDD6 parametersGo
  • Added Hysteresis parameter, min and max values to TprotVDD5 (2.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from VDD5 switch-off to Protection of VDD5.In case of detected over-temperature, only VDD5 will be switched-off for both TprotVDD5 parametersGo
  • Added VDD3/5 end-value to test condition for the dVDD35/dt parameter (3.11) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVDD3/5 (3.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Global shutdown to Protection of VDD3/5, treated as global thermal shutdown (shutdown for all regulators) for both TprotVDD3/5 parametersGo
  • Added test condition to the dVDD1/dt parameter (A4.14) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added VSOUT1 text to test condition for VSOUT1 parameter (5.1) in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed MVVSOUT1 min and max values from –15 and 15 to –35 and 35 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added min and max values for the Threshold for tracking/non-tracking parameter in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to TprotVSOUT1 (5.13) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from VSOUT1 switch-off to Protection of Sensor Supply. Only VSOUT1 switch-off for both TprotVSOUT1 parametersGo
  • Changed min and max values for VBATP_OVrise parameter from 29.5 and 32.5 to 34.7 and 36.7 (respectively) in the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Deleted VBATP_OVhys (POS 6.6) from the ELECTRICAL CHARACTERISTICS tableGo
  • Changed min and max values for VBATP_OVfall parameter from 29 and 32 to 34.4 and 36.3 (respectively) in the ELECTRICAL CHARACTERISTICS table. Also added test conditionGo
  • Added Hysteresis parameter, min and max values to VDD5_UV (6.8) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed max value for VDD5_OV from 5.5 to 5.45 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter, min and max values to VDD5_OV (6.10) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed min value for VDD3/5_UV with test condition of 3.3-V setting (undervoltage) from 2.97 to 3 in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value for VDD3/5_UV with test condition of 5-V setting (undervoltage) from 4.8 to 4.85 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter for 3.3 and 5 V settings, min and max values to VDD3/5_UV (6.12) in the ELECTRICAL CHARACTERISTICS table. Go
  • Changed max value for VDD3/5_OV with test condition of 3.3-V setting from 3.63 to 3.6 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added Hysteresis parameter for 3.3 and 5 V settings, min and max values to VDD3/5_OV (6.14) in the ELECTRICAL CHARACTERISTICS table. Go
  • Added Hysteresis parameter, min and max values to VDD1_UV (6.16) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VDD1_SENSE pin to Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) for both VDD1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD1_OV (6.17) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VDD1_SENSE pin to Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) for both VDD1_OV parametersGo
  • Added Hysteresis parameter, min and max values to VSOUT1_UV (6.19) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VSFB1 pin to Sensed on VSFB1 pin Relative thresholds are: for both VSOUT1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VSOUT1_UV (6.20) in the ELECTRICAL CHARACTERISTICS table. Changed test condition from Sensed on VSFB1 pin to Sensed on VSFB1 pin Relative thresholds are: for both VSOUT1_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD6_UV (6.22) in the ELECTRICAL CHARACTERISTICS table. Also added test condition for both VDD6_UV parametersGo
  • Added Hysteresis parameter, min and max values to VDD6_OV (6.23) in the ELECTRICAL CHARACTERISTICS table. Also added test condition for both VDD6_OV parametersGo
  • Added test condition to the I_IGN parameter in the the ELECTRICAL CHARACTERISTICS table(7.4)Go
  • Changed I_CAN parameter (7.7) to I_CANWU and added test condition to the ELECTRICAL CHARACTERISTICS tableGo
  • Changed I_CAN_rev (7.8) max value from 1 to –1 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added test condition for ICP (8.2) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added min and max values for fCP (8.3) in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted min value of 11 for the Rdson_ENDRV_NRES (9.2a) parameter in the ELECTRICAL CHARACTERISTICS table Go
  • Added input and logic 1 to the VENDRV_NRES_TH parameter (9.5) description in the ELECTRICAL CHARACTERISTICS tableGo
  • Deleted max value from 500 to 450 for the VENDRV_NRES_TH (9.5) parameter in the ELECTRICAL CHARACTERISTICS table Go
  • Added note reference and test condition to the VDIGIN_LOW parameter (10.2) in the ELECTRICAL CHARACTERISTICS table Go
  • Added note reference and test condition to the VDIGIN_HYST parameter (10.3) in the ELECTRICAL CHARACTERISTICS table. Also added parameter nameGo
  • Changed 10.4 from empty to the RDIAGOUT_AMUX parameter to the ELECTRICAL CHARACTERISTICS table Go
  • Added pin note to the VDIGOUT_HIGH parameter (10.5) in the ELECTRICAL CHARACTERISTICS table Go
  • Added pin note to the VDIGOUT_LOW parameter (10.6) in the ELECTRICAL CHARACTERISTICS table Go
  • Added min and max values for tRSTEXT(0kΩ) (9.4a) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added tWD_pulse parameter to the ELECTRICAL CHARACTERISTICS tableGo
  • Added for MCU error signal monitor to the tERROR_WDI_deglitch parameter (12.1) in the ELECTRICAL CHARACTERISTICS table Go
  • Changed max value for the tERROR_WDI_deglitch parameter (12.1) from 15.75 to 16.25 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added two test conditions to the fSPI parameter (13.1) and removed the single max value of 8 to replace it with the max value for each condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Added two test conditions to the tSPI parameter (13.2) and removed the single min value of 125 to replace it with the min value for each condition in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value for tsusi(13.7) to min value in the ELECTRICAL CHARACTERISTICS table. Also changed parameter description from rising edge to falling edge of SCLKGo
  • Changed min value from 250 to 788 for the thlcs parameter (13.10) in the ELECTRICAL CHARACTERISTICS table. Also added NCS high text to parameter descriptionGo
  • Added test condition to the fSysclk parameter (11.1) in the ELECTRICAL CHARACTERISTICS tableGo
  • Added SDO transition from tri-state to td1 parameter (13.6) description in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of td1 from 30 to 53.3 in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of td2 from 30 to 85.7 in the ELECTRICAL CHARACTERISTICS table. parameter description from falling edge to rising edge of SCLKGo
  • Changed ttri parameter (13.11) description from Hi-Z state to tristate in the ELECTRICAL CHARACTERISTICS tableGo
  • Changed max value of ttri (13.11) from 15 to 25 in the ELECTRICAL CHARACTERISTICS tableGo
  • Added td2 to right side of SPI Timing Parameters diagramGo
  • Added the SPI SDO Buffer Source/Sink Current graph after the ELECTRICAL CHARACTERISTICS tableGo
  • Changed block diagramGo
  • Added condition for when the N-channel MOSFET turns on to the second paragraph in the VDD6 Buck Switch Mode Power Supply section Go
  • Deleted clearing out of SAFETY_STAT from re-enable VDD5 paragraph and changed SENS_CTRL bit from 4 to D4 in the VDD5 Linear Regulator sectionGo
  • Added the default VDD1 paragraph to the end of the VDD1 Linear Regulator sectionGo
  • Added sentence to the first paragraph in the VSOUT1 Linear Regulator section describing what occurs after completion of the VDDx ramp-upGo
  • Changed tracking offset from ±15 to ±35 in the VSOUT1 Linear Regulator sectionGo
  • Added SPI command setting to the seventh paragraph in the VSOUT1 Linear Regulator sectionGo
  • Added DIAGNOSTIC state text to the Wake-Up sectionGo
  • Changed second paragraph in the Wake-Up section: changed edge-sensitive to level-sensitive and pulse duration to deglitch time.Go
  • Added during a power-up event to the Reset Extension section and removed VDD1 from the descriptionGo
  • Deleted open-connect and RESET state sentence from the last paragraph in the Reset Extension sectionGo
  • Changed Power-Up and Power-Down Behavior image in the Power-Up and Power-Down Behavior sectionGo
  • Added notes to theIGN Power Latch and POST-RUN Reset image in the Power-Up and Power-Down Behavior sectionGo
  • Deleted reset driver from ENDRV bullet in the Safety Functions and Diagnostics Overview section Go
  • Added the Voltage Monitoring Overview table and table reference to the Voltage Monitor (VMON) sectionGo
  • Added the Internal Error Signals tableGo
  • Deleted loss-of-power note and cleared-latched bullet from the clock failure list in the Loss-of-Clock Monitor (LCMON) sectionGo
  • Added SPI register bit to the latched bullet in the clock failure list in the Loss-of-Clock Monitor (LCMON) sectionGo
  • Added ABIST case paragraphs following the Analog BIST Run States imageGo
  • Moved Logic Built-In Self-Test (LBIST) section from after DMUX tables and added initialized registers listGo
  • Deleted VDD5 and VSOUT1 supplies from first paragraph of the Junction Temperature Monitoring and Current Limiting section Go
  • Added VSOUT1 supplies paragraph to the Junction Temperature Monitoring and Current Limiting sectionGo
  • Added Go
  • Deleted STANDBY State text from the Junction Temperature Monitoring and Current Limiting section and changed to regulated supplies. Also added ENDRV pinGo
  • Changed third paragraph of the Junction Temperature Monitoring and Current Limiting section to include NRES asserted low and VDD5 reenable Go
  • Added Thermal and Overcurrent Protect Overview table and table reference to the Junction Temperature Monitoring and Current Limiting sectionGo
  • Added analog and digital signals and notes to the Diagnostic Output Pin DIAG_OUT image in the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added added disabled state description for the DIAG_OUT pin in the last paragraph of the Diagnostic Output Pin DIAG_OUT sectionGo
  • Added accuracy and corresponding table note to the voltage range column in the Analog MUX Selection tableGo
  • Added ± percentage to the divide ratio values (except for MAIN_BG and VMON_BG) the Analog MUX Selection tableGo
  • Changed the DIAG_MUX_SEL column and header in the Analog MUX Selection tableGo
  • Added the max output resistance column to the Analog MUX Selection tableGo
  • Changed VSFB1 divide ratio from 1 to 4 in the Analog MUX Selection Table Go
  • Added the voltage/signal name for signal number A.7 from BG1 to MAIN_BG in the Analog MUX Selection tableGo
  • Added additional text and note to further explain the Analog MUX Selection Table Go
  • Added second paragraph to the Digital MUX (DMUX) sectionGo
  • Added diagnostic check text, Diagnostic MUX Output state (by MUX_OUT bit), and MUX interconnect check section after DMUX tablesGo
  • Changed the Watchdog Enable Function image in the WDT Fail Counter, WDT Status, and WDT Fail Event sectionGo
  • Added watchdog fail counter text after the Watchdog Status for Fail Counter Value Range tableGo
  • Changed trigger events paragraph (third) in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added SPI register names and DIAGNOSTIC state to the open and close window programming sentence in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added the WDTI window sequencing and SPI SW_LOCK paragraphs in the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added the WDTI rising edge paragraph in the WDTI Configuration with External Trigger Input (Default Mode) section and added tWD_pulse filter time paragraphGo
  • Added image to the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Added image to the WDTI Configuration with External Trigger Input (Default Mode) sectionGo
  • Deleted ASIC reference in the first paragraph of the Watchdog Question /and Answer Configuration Through SPI sectionGo
  • Added starts a new watchdog token-response sequence run to the no-response event description in paragraph four of the Watchdog Question /and Answer Configuration Through SPI sectionGo
  • Added 4-bit word bullet to the Watchdog Token Request definition list in the Watchdog-Timer-Related SPI Event Definitions sectionGo
  • Added 32-bit word bullet to the Watchdog Token Timer Request definition list in the Watchdog-Timer-Related SPI Event Definitions sectionGo
  • Added Watchdog Token-Response Sequence Run section to replace the Watchdog Timer Configuration for Question and Answer Configuration sectionGo
  • Changed the WDT Token and Response Sequence Run image in the Watchdog Token-Response Sequence Run sectionGo
  • Added the 4-bit question paragraph to the Watchdog Token Value Generation (or Watchdog Question Generation) sectionGo
  • Added the Watchdog TOKEN Generation image and following text in the Watchdog Timer Configuration for Question and Answer Configuration sectionGo
  • Added Answer Comparison and Reference Answer sectionGo
  • Changed WDT answer column header names - switched response 0 and response 3, switched response 2 and response 1 in the Set of 4-Bit WD Token Values and Corresponding 8-Bit Responses table. Added token registerDevice Configuration Register Protection name and value to token column.Go
  • Added Watchdog Token-Response Sequence Run and WDT_STATUS Register Updates sectionGo
  • Added activation and deactivation paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added DIAGNOSTIC and ACTIVE state paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added deglitched and synchronized paragraph in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added ERROR/WDI pin implementation text in the MCU Error Signal Monitor (MCU ESM) sectionGo
  • Added the first paragraph in the PWM Mode section and added the detect and no detect statementsGo
  • Added monitoring lists to the PWM Mode sectionGo
  • Changed register setting text for the ERROR_PIN_FAIL bit from error-pin signaling failure to system clock detection to the PWM Mode sectionGo
  • Added CFG_CRC_ERR flag text to the Device Configuration Register Protection section Go
  • Changed CRC-8 polynomial from X8 + X7 + X6 + X4 + X2 + 1 to X8 + X2 + X1 + 1 in the Device Configuration Register Protection sectionGo
  • Added 64-bit string text and protected registers list in the Device Configuration Register Protection sectionGo
  • Added CRC Bus Structure table in the Device Configuration Register Protection sectionGo
  • Added CRC calculation text, image, and table in the Device Configuration Register Protection sectionGo
  • Added EEPROM CRC check and list of steps in the Device Configuration Register Protection sectionGo
  • Changed the Reset and Enable Circuit image in the Enable and Reset Driver Circuit sectionGo
  • Added ENDRV pulled low paragraph to the Enable and Reset Driver Circuit sectionGo
  • Changed timing-response diagram description from RESET condition to any VDDx UV or OV condition in the Enable and Reset Driver Circuit sectionGo
  • Added RESET condition image in the Enable and Reset Driver Circuit section and replaced it with the any VDDx UV or OV condition imageGo
  • Changed Device Controller State Diagram imageGo
  • Added Internal NPOR (power-on reset) bullet item in the STANDBY STATE sectionGo
  • Changed IGN and CANWU driven low bullet item to deglitched IGN, IGN_PWRL, and CANWU_L with values in the STANDBY STATE sectionGo
  • Added device error count text to the SAFE state bullet in the RESET STATE listGo
  • Deleted the ACTIVE state bullet in the RESET STATE listGo
  • Added VDD5 sub-bullet in the RESET STATE listGo
  • Added watchdog fail counter text to the watchdog reset sub-bullet in the RESET STATE listGo
  • Added ramping up sub-bullet to the first item in the RESET STATE listGo
  • Added RESET State transition paragraph to the RESET STATE listGo
  • Added NRES pulled up to the Enters RESET state bullet in the DIAGNOSTIC STATE listGo
  • Added VSOUT1, watchdog and ERROR/WDI, watchdog failure counter, and ENDRV pin bullets in the DIAGNOSTIC STATE listGo
  • Added DIAG_EXIT_MASK and DIAG_EXIT text to the end of the DIAGNOSTIC STATE listGo
  • Changed two bullets in the ACTIVE STATE list and added three additional bulletsGo
  • Added uncontrolled transition sub-bullet to the enters DIAGNOSTIC state bullet in the SAFE STATE listGo
  • Added ACTIVE state read-back error, stays in Safe state, NRES, and VDDx bullets in the SAFE STATE listGo
  • Added STATE TRANSITION PRIORITIES sectionGo
  • Deleted Enters from RESET, DIAGNOSTIC, or ACTIVE state after ABIST or LBIST failure bullet from the SPI 4-pin list in the SPI Interface sectionGo
  • Changed speed from 10 to 6 Mbit/s in the SPI Interface sectionGo
  • Added minimum time sentence to paragraph after the SPI Command Transfer Phase table Go
  • Deleted paragraph describing the possibility of mixing two access modes in the SPI Data-Transfer Phase sectionGo
  • Added minimum time sentence to paragraph after the SPI Data-Transfer Phase tableGo
  • Added status bit paragraph and note after the Device Status Flag Byte Response tableGo
  • Added 8-bit hex column to the SPI Command TableGo
  • Changed D5 from 0 to 1 in the DEV_REV Register tableGo
  • Changed D0 from 0 to 1 in the DEV_REV Register tableGo
  • Changed D0 from 0 to 1 in the DEV_ID Register tableGo
  • Changed reset value text to D[1] and D[0] descriptions in the DEV_STATE Register tableGo
  • Changed D6 from MASK_VDD_OV and 1 to nMASK_VDD_UV_OV and 0 in the DEV_CFG1 Register tableGo
  • Added ground and no ground to the SEL_VDD3/5 description for both 5 V and 3.3 V in the DEV_CFG1 Register tableGo
  • Added value in RESET State text in the DEV_CFG1 Register tableGo
  • Added READ-ONLY the DEV_CFG1 Register tableGo
  • Added after first start-up text to D[6] if VDD1 text in the DEV_CFG1 Register tableGo
  • Switched the names of D5 and D4 in DEV_CFG2 Register tableGo
  • Changed EN_VDD3/5_OT description by removing extra text after set to 1 and adding two more bullets in the DEV_CFG2 Register tableGo
  • Changed read/writable text for D[3:0] in the DEV_CFG2 Register tableGo
  • Changed AVDD_VMON_ERR description from error status to power-good status in the VMON_STAT_1 Register tableGo
  • Changed set to 1 text of D[1] in the VMON_STAT_1 Register table from when error is detected to when voltage monitor < main band gap Go
  • Changed set to 1 text of D[0] in the VMON_STAT_1 Register table froGo
  • Changed m when error is detected to when voltage monitor > main band gap Go
  • Changed name of D6 from VDD3_ILIM to VDD3_5_ILIM in the SAFETY_STAT_1 Register tableGo
  • Added note to D[7] description in the SAFETY_STAT_1 Register tableGo
  • Added EEPROM bullet to D[5] description in the SAFETY_STAT_2 Register tableGo
  • Added DIAGNOSTIC and ACTIVE State text to D[2:0] default bullet in the SAFETY_STAT_2 Register tableGo
  • Added cleared to text to the D[5] description in the SAFETY_STAT_3 Register tableGo
  • Changed D7 and D6 from 1 to 0 in the SAFETY_STAT_4 Register tableGo
  • Changed name of D0 from TRIM_ERR to TRIM_ERR_VMON in the SAFETY_STAT_4 Register tableGo
  • Added cleared to bullet and note to D[7:6] description in the SAFETY_STAT_4 Register tableGo
  • Changed set to text to include error-signal monitoring in the D[3] description in the SAFETY_STAT_4 Register tableGo
  • Added ERROR_PIN_FAIL text to D[3] cleared description in the SAFETY_STAT_4 Register tableGo
  • Added Watchdog Fail Counter text to the D[2] set to and cleared to descriptions in the SAFETY_STAT_4 Register tableGo
  • Deleted SPI read access from D[1]cleared to description in the SAFETY_STAT_4 Register table Go
  • Changed SPI read access to NPOR in the D[0]cleared to description in the SAFETY_STAT_4 Register table Go
  • Changed D4 from 1 to 0 and D1 and D0 from 0 to 1 in the SAFETY_STAT_5 Register tableGo
  • Changed threshold from max to min for the 0000 setting description in the SAFETY_ERR_CFG Register tableGo
  • Changed D7 and D6 from 1 to 0 in the SAFETY_BIST_CTRL Register tableGo
  • Changed D3 from LOCLK_EN to RSV in the SAFETY_BIST_CTRL Register tableGo
  • Added ACTIVE state bullet to D[7:6] description in the SAFETY_BIST_CTRL Register tableGo
  • Added DIAGNOSTIC and ACTIVE states to D[5] description in the SAFETY_BIST_CTRL Register tableGo
  • Changed D4 from NO_WRST to RSV in the SAFETY_CHECK_CTRL Register tableGo
  • Added DEV_CFG2 and DEV_CFG1 to D[7] list of protected registers in the SAFETY_CHECK_CTRL Register tableGo
  • Added device state, ENDRV and NRES to D[6] description in the SAFETY_CHECK_CTRL Register tableGo
  • Changed D[3] from not read/writable to read/writable in the SAFETY_CHECK_CTRL Register tableGo
  • Added ERROR_PIN_FAIL sub-bullet to D[2] descriptionin the SAFETY_CHECK_CTRL Register table Go
  • Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register tableGo
  • Changed D2 from RSV to DIS_NRES_MON in the SAFETY_FUNC_CFG Register tableGo
  • Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register tableGo
  • Added SAFE state-time sub-bullet to the D[7] description in the SAFETY_FUNC_CFG Register tableGo
  • Changed D[6] description from error-pin to Error-Signal Monitor in the SAFETY_FUNC_CFG Register tableGo
  • Deleted watchdog pin from the D[6] description in the SAFETY_FUNC_CFG Register tableGo
  • Added note text to the D[4] description in the SAFETY_FUNC_CFG Register tableGo
  • Added STANDBY state text to the D[4] description in the SAFETY_FUNC_CFG Register tableGo
  • Deleted enabling/disabling the watchdog bullet from the D[3] description in the SAFETY_FUNC_CFG Register tableGo
  • Added bullets to the D[2] description in the SAFETY_FUNC_CFG Register tableGo
  • Changed D[1] from not read/writable to read/writable in the SAFETY_FUNC_CFG Register tableGo
  • Added READ-ONLY bullet, RESET STATE sub-bullet, and connected and not-connected text to the D[0] description in the SAFETY_FUNC_CFG Register tableGo
  • Added ERROR/WDI and SAFE state text to the D[5] set to description in the SAFETY_ERR_STAT Register tableGo
  • Added WD_RST_EN text to D[4] set to description in the SAFETY_ERR_STAT Register tableGo
  • Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register tableGo
  • Added equation and oscillator text to the SAFETY_ERR_PWM_H Register table descriptionGo
  • Changed D4, D2, and D0 from 0 to 1 in the SAFETY_ERR_PWM_L Register descriptionGo
  • Added equations and oscillator text to the SAFETY_ERR_PWM_H Register table descriptionGo
  • Changed D4 from 1 to 0 in theSAFETY_PWD_THR_CFG Register tableGo
  • Changed _THR to PWD names for D3:D0 in theSAFETY_PWD_THR_CFG Register tableGo
  • Changed D7, D5, and D3 from 1 to 0 in the SAFETY_CFG_CRC Register tableGo
  • Changed D4 from 0 to 1 in the SAFETY_CFG_CRC Register tableGo
  • Changed D[7] description from high-impedance to tri-stated in the DIAG_CFG_CTRL Register tableGo
  • Added SDO diagnostics from D[1:0] description to the D[6] description in the DIAG_CFG_CTRL Register tableGo
  • Changed D2 from 1 to 0 in the WDT_TOKEN_FDBCK Register table Go
  • Added bullets to the D[7:4] description in the WDT_TOKEN_FDBCK Register table Go
  • Added new TOKEN seed bullet and sub-bullets to the D[3:0] description in the WDT_TOKEN_FDBCK Register table Go
  • Changed D6:D0 from 0 to 1 in the WDT_WIN1_CFG Register table Go
  • Changed D4:D3 from 0 to 1 in the WDT_WIN2_CFG Register tableGo
  • Changed D7 from 0 to 1 in the WDT_TOKEN_VALUE Register tableGo
  • Changed MCU sub-bullet from D[7] description to replace Q&A sub-bullet in the D[3:0] description of the WDT_TOKEN_VALUE Register tableGo
  • Changed D7:D6 from 0 to 1 in the WDT_STATUS Register tableGo
  • Changed D7:DF from RSV to WD_WRONG_CFG in the WDT_STATUS Register tableGo
  • Changed set to text of the D[5] description in the WDT_STATUS Register table Go
  • Changed D[4] note from recommendation to clear bit to remains set to 1 in the SENS_CTRL Register table Go
  • Changed Typical Application Diagram imageGo