SLVT216 July   2024 TPS546C25 , TPS546E25

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2General
    1. 2.1 No Immediate Disable From Soft Start
    2. 2.2 Power Stage Over Temperature Protect
    3. 2.3 Negative Current Limit
    4. 2.4 Programmable Reference DAC gain low
  6. 3Security
    1. 3.1 Standard Write Protection Does Not Work on Secondary Device
    2. 3.2 Device Does Not NACK Incorrect Passkey Per PMBus 1.5
    3. 3.3 Device Does Not Alternate Between Lock and Unlock When Passkey is Written Multiple Times
  7. 4Stacking Interface and Operation of P2_PLUS_Commands
    1. 4.1 Inconsistent P2_PLUS_(various) NACKing by Secondary Device
    2. 4.2 IOUT_OC_FAULT_LIMIT Not Readable on Secondary Device Via P2_PLUS_READ
    3. 4.3 STACK_CONFIG Writable When Should be Read Only
    4. 4.4 Secondary Device ACK's Write to Some Read-Only Registers
    5. 4.5 Secondary Device NACKs All P2_PLUS_WRITE Commands With PHASE = 0xFF
    6. 4.6 Secondary Asserts IVD for P2_PLUS_READ of ALERT_MASK_(various) With PHASE = 0xFF
    7. 4.7 Secondary Device NACKing P2_PLUS_(various) With Valid PHASE
    8. 4.8 Invalid PAGE is ACKed for P2_PLUS_READ Command
  8. 5PMBUS
    1. 5.1 READ_IOUT Data Format is Not Correct
    2. 5.2 OPERATION Not changing VOUT_SOURCE When OFF = b’1
    3. 5.3 PIN_DETECT_OVERRIDE Power-On Source Control Inverted
    4. 5.4 PIN_DETECT_OVERRIDE Bit 15 OVRD_STACK is Not Working Correctly
    5. 5.5 STATUS_OTHER FRST_2_ALRT Does Not Assert STATUS_BYTE or STATUS_WORD Other Bit 0
    6. 5.6 Clamping VOUT by VREF Range Not setting VOUT_MAX_MIN in STATUS_VOUT
  9. 6Summary
  10. 7References

5.6 Clamping VOUT by VREF Range Not setting VOUT_MAX_MIN in STATUS_VOUT

  • Description: If the Output voltage is programmed above the maximum range of the reference DAC voltage, the output voltage is clamped to 0.75V / VOUT_SCALE_LOOP, but the VOUT_MAX_MIN bit in STATUS_VOUT is not set.
  • System Impact: No status warning bit set indicating that the programmed VOUT was not achieved.
  • Workaround or Mitigation: Use the correct VOUT_SCALE_LOOP value to set output voltage. Check VOUT using READ_VOUT after setting VOUT.
  • Disposition: Design fix planned for final silicon.