SLVU491A November   2011  – October 2021 TPS54294

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
    2. 3.2 Output Filter and Closed-Loop Response
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Efficiency
      1. 4.3.1 Efficiency of Converter 1
      2. 4.3.2 Efficiency of Converter 2
    4. 4.4 Load Regulation
      1. 4.4.1 Load Regulation of Converter 1
      2. 4.4.2 Load Regulation of Converter 2
    5. 4.5 Line Regulation
      1. 4.5.1 Line Regulation Converter 1
      2. 4.5.2 Line Regulation Converter 2
    6. 4.6 Load Transient Response
      1. 4.6.1 Load Transient Response Converter 1
      2. 4.6.2 Load Transient Response Converter 2
    7. 4.7 Output Voltage Ripple
      1. 4.7.1 Output Voltage Ripple Converter 1
      2. 4.7.2 Output Voltage Ripple Converter 2
    8. 4.8 Input Voltage Ripple
    9. 4.9 Start-Up and Shutdown
      1. 4.9.1 Start-Up and Shutdown Converter 1
      2. 4.9.2 Start-Up and Shutdown Converter 2
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 Reference
  8. 7Revision History

5.1 Layout

The board layout for the TPS54294EVM is shown in Figure 5-1 through Figure 5-6. The top layer contains the main power traces for VIN and VOUTx. Also on the top layer are connections for the pins of the TPS54294 and a large area filled with ground. Many of the signal traces also are located on the top side. The input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points, and all of the assembled components are located on the top side. An analog ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a single point on the top layer near the IC. The other layers are primarily power ground but the bottom layer has some traces to connect the test points for SSx and ENx.

GUID-2A978449-566E-4B3D-84E3-037F2B864D75-low.gifFigure 5-1 Top Assembly
GUID-0ECABDED-7E6C-4B47-981A-CE6D1B56D1BA-low.gifFigure 5-2 Top Layer
GUID-D7517C0A-EA86-4ECF-84C2-6DE5429E4B35-low.gifFigure 5-3 Internal 1 Layer
GUID-98F188B2-4D2D-436C-814E-BC6EA8399D0F-low.gifFigure 5-4 Internal 2 Layer
GUID-B727D6F5-45EF-4BE5-8C1D-E1DAE3AC89E3-low.gifFigure 5-5 Bottom Layer
GUID-EA5264F8-51D6-4A0F-A58B-5307F7C951DA-low.gifFigure 5-6 Bottom Assembly