SLVUAW9C September   2016  – February 2020 UCD90320

 

  1.   UCD90320 Sequencer and System Health Controller PMBus Command Reference
    1.     Trademarks
    2. 1  PMBus Specification
      1. 1.1 Manufacturer Specific Status (STATUS_MFR_SPECIFIC)
    3. 2  Data Formats
      1. 2.1 Data Format for Output Voltage Parameters
      2. 2.2 Data Format for Other Parameters
      3. 2.3 Distinguishing Between Linear Data Formats
      4. 2.4 Translation, Quantization, and Truncation
      5. 2.5 8-Bit Time Encoding
    4. 3  Memory Model
    5. 4  Alert Response Address Support
    6. 5  Supported PMBus Commands
    7. 6  Implementation Details for PMBus Core Commands
      1. 6.1  (00h) PAGE
      2. 6.2  (01h) OPERATION
      3. 6.3  (11h) STORE_DEFAULT_ALL
      4. 6.4  (12h) RESTORE_DEFAULT_ALL
      5. 6.5  (1Bh) SMBALERT_MASK
      6. 6.6  (20h) VOUT_MODE
      7. 6.7  (38h) IOUT_CAL_GAIN
      8. 6.8  (41h – 69h) xxx_FAULT_RESPONSE
      9. 6.9  (62h) TON_MAX_FAULT_LIMIT
      10. 6.10 (66h) TOFF_MAX_WARN_LIMIT
      11. 6.11 (80h) STATUS_MFR_SPECIFIC
      12. 6.12 (81h) STATUS_FAN_1_2 and (82h) STATUS_FAN_3_4
      13. 6.13 (8Dh) READ_TEMPERATURE_1
      14. 6.14 (8Eh) READ_TEMPERATURE_2
      15. 6.15 (90-93h) FAN_SPEED_1 Through FAN_SPEED_4
      16. 6.16 (ADh) IC_DEVICE_ID
      17. 6.17 (AEh) IC_DEVICE_REV
    8. 7  Input and Output Pin Configuration
    9. 8  PWM Configuration
    10. 9  Implementation Details for User Data Commands
      1. 9.1 (B5h) BLACK_BOX_FAULT_INFO (USER_DATA_05)
        1. 9.1.1 Fault Info
      2. 9.2 (B6h) BLACK_BOX_FAULT_RAILS_WARNING(USER_DATA_06)
      3. 9.3 (B7h) BLACK_BOX_LOG_RAILS_VALUE(USER_DATA_07)
      4. 9.4 (B8h) RAIL_PROFILE(USER_DATA_08)
        1. 9.4.1 Number Profile
        2. 9.4.2 Profile Index
      5. 9.5 (B9h) RAIL_STATE (USER_DATA_09)
    11. 10 Implementation Details for Manufacturer-Specific Commands
      1. 10.1  (D0h) FAULT_PIN_CONFIG (MFR_SPECIFIC_00)
        1. 10.1.1 Fault Pin Configuration
        2. 10.1.2 Page Mask
        3. 10.1.3 Other Mask
      2. 10.2  (D1h) VOUT_CAL_MONITOR (MFR_SPECIFIC_01)
      3. 10.3  (D2h) SYSTEM_RESET_CONFIG (MFR_SPECIFIC_02)
        1. 10.3.1 GPI Flags
        2. 10.3.2 Page Flags
        3. 10.3.3 De-Assert When Power-Good
        4. 10.3.4 Assert When NOT Power-Good
        5. 10.3.5 Assert When Watchdog Timeout
        6. 10.3.6 Delay Time
        7. 10.3.7 Pulse Time
        8. 10.3.8 GPI Tracking
        9. 10.3.9 Reset Pin Configuration
      4. 10.4  (D3h) SYSTEM_WATCHDOG_CONFIG (MFR_SPECIFIC_03)
        1. 10.4.1 Enable
        2. 10.4.2 Watch System Reset Pin
        3. 10.4.3 Max Fan Speed With Timeout
        4. 10.4.4 Disable Until System Reset Release
        5. 10.4.5 Start Time
        6. 10.4.6 Input Pin (WDI) Configuration
        7. 10.4.7 Reset Period
        8. 10.4.8 Output Pin (WDO) Configuration
      5. 10.5  (D4h) SYSTEM_WATCHDOG_RESET (MFR_SPECIFIC_04)
      6. 10.6  (D5h) MONITOR_CONFIG (MFR_SPECIFIC_05)
      7. 10.7  (D6h) NUM_PAGES (MFR_SPECIFIC_06)
      8. 10.8  (D7h) RUN_TIME_CLOCK (MFR_SPECIFIC_07)
      9. 10.9  (D8h) RUN_TIME_CLOCK_TRIM (MFR_SPECIFIC_08)
      10. 10.10 (D9h) ROM_MODE (MFR_SPECIFIC_09)
      11. 10.11 (DAh) USER_RAM_00 (MFR_SPECIFIC_10)
      12. 10.12 (DBh) SOFT_RESET (MFR_SPECIFIC_11)
      13. 10.13 (DCh) RESET_COUNT (MFR_SPECIFIC_12)
      14. 10.14 (DDh) PIN_SELECTED_RAIL_STATES (MFR_SPECIFIC_13)
        1. 10.14.1 System State Enables
        2. 10.14.2 Soft-Off Enables
        3. 10.14.3 System State
      15. 10.15 (DEh) RESEQUENCE (MFR_SPECIFIC_14)
      16. 10.16 (DFh) CONSTANTS (MFR_SPECIFIC_15)
      17. 10.17 (E0h) PWM_SELECT (MFR_SPECIFIC_16)
      18. 10.18 (E1h) PWM_CONFIG (MFR_SPECIFIC_17)
      19. 10.19 (E2h) PARM_INFO (MFR_SPECIFIC_18)
      20. 10.20 (E3h) PARM_VALUE (MFR_SPECIFIC_19)
      21. 10.21 (E4h) TEMPERATURE_CAL_GAIN (MFR_SPECIFIC_20)
      22. 10.22 (E5h) TEMPERATURE_CAL_OFFSET (MFR_SPECIFIC_21)
      23. 10.23 (E9h) FAULT_RESPONSES (MFR_SPECIFIC_25)
        1. 10.23.1 Fault Response Bytes
        2. 10.23.2 Resequence
        3. 10.23.3 Time Between Retries
        4. 10.23.4 Maximum Glitch Time for Voltage Faults
        5. 10.23.5 Maximum Glitch Time for Non-Voltage Faults
      24. 10.24 (EAh) LOGGED_FAULTS (MFR_SPECIFIC_26)
        1. 10.24.1 Command Format
        2. 10.24.2 Non-Paged Faults
        3. 10.24.3 GPI Faults
        4. 10.24.4 Page-Dependent Faults
      25. 10.25 (EBh) LOGGED_FAULT_DETAIL_INDEX (MFR_SPECIFIC_27)
      26. 10.26 (ECh) LOGGED_FAULT_DETAIL (MFR_SPECIFIC_28)
      27. 10.27 (EDh) LOGGED_PAGE_PEAKS (MFR_SPECIFIC_29)
      28. 10.28 (EEh) LOGGED_COMMON_PEAKS (MFR_SPECIFIC_30)
      29. 10.29 (EFh) LOGGED_FAULT_DETAIL_ENABLES (MFR_SPECIFIC_31)
      30. 10.30 (F0h) EXECUTE_FLASH (MFR_SPECIFIC_32)
      31. 10.31 (F1h) SECURITY (MFR_SPECIFIC_33)
        1. 10.31.1 Enabling Security
        2. 10.31.2 Disabling Security
        3. 10.31.3 Reading This Command
      32. 10.32 (F2h) SECURITY_BIT_MASK (MFR_SPECIFIC_34)
      33. 10.33 (F3h) MFR_STATUS (MFR_SPECIFIC_35)
      34. 10.34 (F4h) GPI_FAULT_RESPONSES (MFR_SPECIFIC_36)
        1. 10.34.1 Fault Responses Byte
        2. 10.34.2 Time Between Retries
        3. 10.34.3 Max Glitch Time for GPI
        4. 10.34.4 GPI Number Rail Profile Pin Selection
        5. 10.34.5 Block Out Period for Profile
      35. 10.35 (F5h) MARGIN_CONFIG (MFR_SPECIFIC_37)
      36. 10.36 (F6h) SEQ_CONFIG (MFR_SPECIFIC_38)
        1. 10.36.1  Enable Pin Configuration
        2. 10.36.2  GPI Sequence On Dependency Mask
        3. 10.36.3  GPI Sequence Off Dependency Mask
        4. 10.36.4  Sequencing Timeout Configuration
        5. 10.36.5  Sequencing On Timeout
        6. 10.36.6  Sequencing Off Timeout
        7. 10.36.7  Page Sequence On Dependency Mask
        8. 10.36.8  Page Sequence Off Dependency Mask
        9. 10.36.9  Fault Slaves Mask
        10. 10.36.10 GPO Sequence On Sependency Mask
        11. 10.36.11 GPO Sequence Off Sependency Mask
      37. 10.37 (F7h) GPO_CONFIG_INDEX (MFR_SPECIFIC_39)
      38. 10.38 (F8h) GPO_CONFIG (MFR_SPECIFIC_40)
        1. 10.38.1  Output Pin Configuration
        2. 10.38.2  Assert Delay Enable
        3. 10.38.3  De-Assert Delay Enable
        4. 10.38.4  Invert OR Output
        5. 10.38.5  Ignore Inputs During Delay
        6. 10.38.6  Invert AND Output
        7. 10.38.7  State Machine Mode Enable
        8. 10.38.8  High Resolution Delay Count
        9. 10.38.9  9 Millisecond Delay
        10. 10.38.10 Status Mask
        11. 10.38.11 Status Inversion Mask
        12. 10.38.12 GPI Mask
        13. 10.38.13 GPI Inversion Mask
        14. 10.38.14 GPO Mask
        15. 10.38.15 GPO Inversion Mask
        16. 10.38.16 Status Type Select
        17. 10.38.17 GPO Configuration Examples
      39. 10.39 (F9h) GPI_CONFIG (MFR_SPECIFIC_41)
        1. 10.39.1 GPI Pin Configuration
          1.        Table 1. Fault Enable Bits
        2. 10.39.2 Sequence Timeout Pin Selection
        3. 10.39.3 Latched Statuses Clear Pin Selection
        4. 10.39.4 MRG_EN Pin Selection
        5. 10.39.5 MRG_LOW_nHIGH Pin Selection
        6. 10.39.6 Debug Mode Pin Selection
      40. 10.40 (FAh) GPIO_SELECT (MFR_SPECIFIC_42)
      41. 10.41 (FBh) GPIO_CONFIG (MFR_SPECIFIC_43)
      42. 10.42 (FCh) MISC_CONFIG (MFR_SPECIFIC_44)
        1. 10.42.1 Miscellaneous Configuration Byte
        2. 10.42.2 Time Between Resequences
        3. 10.42.3 External Reference Voltage
        4. 10.42.4 Resequence_rails_mask
      43. 10.43 (FDh) DEVICE_ID (MFR_SPECIFIC_45)
    12. 11 Range Checking and Limits
    13. 12 Glossary

10.38.7 State Machine Mode Enable

When this bit is set, only one of the AND path is used at a given time. When the GPO logic result is currently TRUE, AND path 0 is used until the result becomes FALSE. When the GPO logic result is currently FALSE, AND path 1 is used until the result becomes TRUE. This logic provides a very simple state machine and allows for more complex logical combinations.

NOTE

The device initially evaluates AND path 0. If it is TRUE, it continues to evaluate AND path 0. If it is FALSE, it begins evaluating AND path 1.
state_machine_slvuaw9.gifFigure 6. State Machine

For example, for a GPO to be asserted if two GPI pins are both asserted and stay asserted until both GPIs are de-asserted, we need to apply an AND operation when the GPO is de-asserted and apply an OR operation when the GPO is asserted. This behavior is shown in Figure 7, where waveform 1 is a GPO, waveform 2 is a GPI, and waveform 3 is a GPO.

waveform_1_slvuaw9.pngFigure 7. Example of State Machine

This behavior is configured by setting the “State Machine Mode Enable”, configuring AND path 0 as (GPI1’ AND GPI2’)’, and configuring AND path 1 as (GPI1 AND GPI2).