SLVUBT8B November   2020  – June 2022 LP8764-Q1 , TPS6594-Q1

 

  1.   Scalable PMIC's GUI User’s Guide
  2.   Trademarks
  3. 1 Introduction
  4. 2 Supported Features
  5. 3 Revisions
  6. 4 Overview
  7. 5 Getting Started
    1. 5.1 Finding the GUI
    2. 5.2 Downloading the Required Software
    3. 5.3 Launching the GUI
    4. 5.4 Connecting to a PMIC
  8. 6 Quick-start Page
    1. 6.1 Device Scan Results
    2. 6.2 Configuration and Monitoring
      1. 6.2.1 System Info
      2. 6.2.2 BUCK
      3. 6.2.3 LDO
      4. 6.2.4 GPIO
      5. 6.2.5 Interrupts
      6. 6.2.6 Miscellaneous Settings
      7. 6.2.7 Advanced
  9. 7 Register Map Page
  10. 8 NVM Configuration Page
    1. 8.1 Creating a Custom Configuration
      1. 8.1.1 Static Configuration
      2. 8.1.2 Pre-Configurable Mission States (PFSM)
        1. 8.1.2.1 Creating a State Diagram
        2. 8.1.2.2 Global Settings
        3. 8.1.2.3 Power Sequence
          1. 8.1.2.3.1 Power Sequence Resources and Commands
          2. 8.1.2.3.2 Sub-sequences
          3. 8.1.2.3.3 Power Sequence Editing Tools
        4. 8.1.2.4 Trigger Settings
        5. 8.1.2.5 Trigger Priority List
        6. 8.1.2.6 PFSM Validation
    2. 8.2 Program
      1. 8.2.1 Program an Existing NVM Configuration
      2. 8.2.2 NVM Configuration Special Use Case: Changing the Communication Interface
      3. 8.2.3 Lock Option During NVM Programming
  11. 9 NVM Validation Page
  12. 10Watchdog Page
  13. 11Additional Resources
  14. 12Appendix A: Troubleshooting
    1. 12.1 Hardware Platform Not Recognized
    2. 12.2 PMIC Device Not Found
    3. 12.3 I2C2 is configured but not connected
  15. 13Appendix B: Advanced Topics
    1. 13.1 Scripting Window
  16. 14Appendix C: Known Limitations
  17. 15Appendix D: Migration Topics
    1. 15.1 Migrating from LP8764-Q1 PG1.0 to PG2.0
    2. 15.2 Update the PFSM to Include the PFSM_START State
    3. 15.3 Update Timing Delays
    4. 15.4 Update Trigger Priority and Settings
  18. 16Revision History

6.2.5 Interrupts

From the interrupts tab the user can decide to mask or monitor various interrupt sources: State Machine, GPIOs, BUCKs, and so on.

The interrupt status, shown on the right side of Figure 6-8, can be used to monitor the interrupt events. The interrupts are grouped according to function and can be expanded to see each individual interrupt source. TOP LEVEL INTERRUPTS are read only and cannot be cleared. Other interrupts can be cleared at a register or bit level, as indicated by the reset symbol. An ERROR status with a red dot indicates that an interrupt has occurred while a NORMAL status with a green dot indicates that no interrupt has occurred or that the interrupt has been cleared. Typically, gray represents interrupts which are masked.  If an interrupt has a NORMAL status with a gray dot, then this indicates that the interrupt is not applicable for the specified phase configuration. The GUI will ignore any attempt to unmask or generate an interrupt that is not applicable to the device phase configuration.

GUID-D5B155AA-4AEA-42FE-8DA1-802CB67F6007-low.png Figure 6-8 Interrupt Mask and Status