SLVUBT8B November   2020  – June 2022 LP8764-Q1 , TPS6594-Q1

 

  1.   Scalable PMIC's GUI User’s Guide
  2.   Trademarks
  3. 1 Introduction
  4. 2 Supported Features
  5. 3 Revisions
  6. 4 Overview
  7. 5 Getting Started
    1. 5.1 Finding the GUI
    2. 5.2 Downloading the Required Software
    3. 5.3 Launching the GUI
    4. 5.4 Connecting to a PMIC
  8. 6 Quick-start Page
    1. 6.1 Device Scan Results
    2. 6.2 Configuration and Monitoring
      1. 6.2.1 System Info
      2. 6.2.2 BUCK
      3. 6.2.3 LDO
      4. 6.2.4 GPIO
      5. 6.2.5 Interrupts
      6. 6.2.6 Miscellaneous Settings
      7. 6.2.7 Advanced
  9. 7 Register Map Page
  10. 8 NVM Configuration Page
    1. 8.1 Creating a Custom Configuration
      1. 8.1.1 Static Configuration
      2. 8.1.2 Pre-Configurable Mission States (PFSM)
        1. 8.1.2.1 Creating a State Diagram
        2. 8.1.2.2 Global Settings
        3. 8.1.2.3 Power Sequence
          1. 8.1.2.3.1 Power Sequence Resources and Commands
          2. 8.1.2.3.2 Sub-sequences
          3. 8.1.2.3.3 Power Sequence Editing Tools
        4. 8.1.2.4 Trigger Settings
        5. 8.1.2.5 Trigger Priority List
        6. 8.1.2.6 PFSM Validation
    2. 8.2 Program
      1. 8.2.1 Program an Existing NVM Configuration
      2. 8.2.2 NVM Configuration Special Use Case: Changing the Communication Interface
      3. 8.2.3 Lock Option During NVM Programming
  11. 9 NVM Validation Page
  12. 10Watchdog Page
  13. 11Additional Resources
  14. 12Appendix A: Troubleshooting
    1. 12.1 Hardware Platform Not Recognized
    2. 12.2 PMIC Device Not Found
    3. 12.3 I2C2 is configured but not connected
  15. 13Appendix B: Advanced Topics
    1. 13.1 Scripting Window
  16. 14Appendix C: Known Limitations
  17. 15Appendix D: Migration Topics
    1. 15.1 Migrating from LP8764-Q1 PG1.0 to PG2.0
    2. 15.2 Update the PFSM to Include the PFSM_START State
    3. 15.3 Update Timing Delays
    4. 15.4 Update Trigger Priority and Settings
  18. 16Revision History

14 Appendix C: Known Limitations

This section contains known limitations of the GUI and which versions the limitations apply to. Please use the support forums to report any issues or limitations found that are not on the following list.

Table 14-1 GUI Limitation and Relevant Version
Number 1.0.0 2.0.0 3.0.0
1 X X X
2 X X X
3 X X X
4 X X
5 X X X
6 X X X
7 X X
8 X X X
9 X X X
10 X
11 X
12 X X
Table 14-2 GUI Limitations Description
Number Description Workaround
1 NVM validation when including the register CRC can report differences associated with addresses 0x0F4 (CRC_5), 0x0F5 (CRC_6), 0x0FE(CRC_15), and 0x0FF (CRC_16). None. The GUI will report that the NVM files do not match. Inspect the registers and disregard differences associated with these registers. Each piece of silicon can have unique values in CRC related to production information.
2 Modifying Device Type and its configuration (for example, Primary/Secondary, Phase Configuration.. etc) is not recommended after creating PFSM as it may not produce expected results In the case of modifying the phase configuration, remove all references in the PFSM before attempting to change the phase configuration. Changing the device type will require starting from a new or blank template.
3 SPI Hardware connection status displayed in the status bar can be detected incorrectly. Use the register map page to confirm that values other than 0x00 and 0xFF can be read from the device. A dialog message appears to address the same.
4 The GUI does not provide control for multiple SPI Chip Select outputs. None. In multi-device SPI configurations the Chip Select signal from the AEVM needs to be manually moved to each PMIC individually.
5 USB Connections issues with COM ports associated with Bluetooth devices. Disable or remove devices which enumerate as COM ports on the host pc.
6 Enumeration (connecting the USB cable to the AEVM) will attempt to connect to the device with the previous or default settings and may fail to connect. Use the Device Settings and click the Connect to Hardware to update the GUI to the correct connection settings.
7 Programming with register CRC enabled can result in a wrong CRC value. Some user registers are not backed by NVM but are part of the CRC calculation. Program the NVM twice.
8 Targets with SPI interfaces should be connected to the PC after the GUI has been configured to SPI mode. Recycle power to the AEVM after selecting SPI in the GUI.
9 Programming an LP876x-Q1 family device and changing GPIO functionality between nRSTOUT and some other function will result in a temporary loss of the serial interface. Typically, this results in a NACK in I2C and a frame error in SPI. The NACK will be seen by the GUI as an error and the programming sequence will stop. Use the register map page to change the GPIO setting to match the setting in the NVM to be programmed. Reprogramming after the first attempt fails (without power cycling the PMIC) will have the same affect, since the user registers for the GPIO settings were updated by the initial attempt to program.
10 PFSM validation will report a warning in the 'Delay Timings Validation' if the PFSM delay step is not restored at the end of a sequence even if the PMIC will transition to the SAFE_RECOVERY state after the sequence is executed. None. When the PMIC transitions to the SAFE_RECOVERY state the PFSM delay step is restored automatically to the default value. The user can disregard this warning, provided the PMIC transitions to SAFE_RECOVERY. This can be seen in the J721E_TPS6594 template.
11 PFSM validation will report an error in the 'Sequence Length Validation' if the SREG_DELAY instruction is used to create the required timing relationship between the primary and secondary PMICs. None. The SREG_DELAY instruction is a unique delay instruction which can change in value during runtime, depending upon what value is loaded into the SREG. The user can disregard this error provided that the usage of the delay is understood and the timing relationship preserved. This only applies to multi-pmic applications. This can be seen in the J721E_TPS6594 template.
12 BUCK Voltage selection, BUCKx_VOUT1 and BUCKx_VOUT2, is not limited by the BUCK use case. Users must ensure that output voltages selected are within the ranges specified in the datasheet for the given configuration use case.