SLVUBX0A July   2021  – January 2022 TPSM8A28 , TPSM8A29

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
  4. 3Getting Started With the TPSM8A29EVM
    1. 3.1 J1 - Input Voltage Supply Connector
    2. 3.2 J4 and J7 - Positive and Negative Output Connectors
    3. 3.3 J2 - Enable Header
    4. 3.4 J5 - Switching Frequency and Operating Mode
    5. 3.5 J6 - Output Voltage Selection Header
  5. 4Test Point Description
    1. 4.1 TP12 - SS/REF_IN
    2. 4.2 TP14 - VCC
  6. 5Test Setup and Results
    1. 5.1 Startup Procedure
    2. 5.2 Efficiency
    3. 5.3 Load Regulation
    4. 5.4 Line Regulation
    5. 5.5 Output Voltage Ripple
    6. 5.6 Startup and Shutdown
    7. 5.7 Load Transient
    8. 5.8 Bode Plot
  7. 6TPSM8A29EVM Schematic
  8. 7TPSM8A29EVM PCB Layers
  9. 8TPSM8A29EVM Bill of Materials
  10. 9Revision History

5.5 Output Voltage Ripple

This section contains oscilloscope images showing the output voltage ripple under various load and FCCM/DCM conditions. All images taken at 25°C.

Equation 7. VIN = 12 V, VOUT = 1.0 V, COUT = 8x47 μF
GUID-20210405-CA0I-XQH0-G5ZP-XMWPTMMMXDZW-low.png
VIN = 12 V IOUT = 0 A fsw = 600 kHz Internal bias FCCM
Figure 5-21 Output Ripple, VOUT = 1.0 V, VRIPPLE = 6.4 mV
GUID-20210405-CA0I-BVC5-GM8M-6W4VFDHKHQPV-low.png
VIN = 12 V IOUT = 15 A fsw = 600 kHz Internal bias FCCM
Figure 5-22 Output Ripple, VOUT = 1.0 V, VRIPPLE = 7.6 mV
GUID-20210405-CA0I-9BFK-BM3M-P0Z8LP3SNHJC-low.png
VIN = 12 V IOUT = 0 A fsw = 600 kHz Internal bias DCM
Figure 5-23 Output Ripple, VOUT = 1.0 V, VRIPPLE = 20.3 mV
GUID-20210405-CA0I-FRBC-736C-TZWKMN6VN18C-low.png
VIN = 12 V IOUT = 0.5 A fsw = 600 kHz Internal bias DCM
Figure 5-24 Output Ripple, VOUT = 1.0 V, VRIPPLE = 10.4 mV
GUID-20210405-CA0I-DKKH-9KC3-DJXLZCPLM9QT-low.png
VIN = 12 V IOUT = 1 A fsw = 600 kHz Internal bias DCM
Figure 5-25 Output Ripple, VOUT = 1.0 V, VRIPPLE = 8.8 mV