SLVUBX4A November   2020  – February 2022 LP8764-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Getting Started
    1. 2.1 Getting Started: Single EVM
    2. 2.2 Getting Started: Multiple EVM Evaluation
    3. 2.3 GUI Tool
  4. 3EVM Details
    1. 3.1 Terminal Blocks
    2. 3.2 Test Point Descriptions
    3. 3.3 Configuration Headers
    4. 3.4 Stack-up Headers
    5. 3.5 Connectors
    6. 3.6 Dip Switches
    7. 3.7 EVM Control and GPIO
  5. 4Customization
    1. 4.1 Changing the Communication Interface
    2. 4.2 Changing the Phase Configuration
  6. 5Schematic, Layout, and Bill of Materials
  7. 6Additional Resources
  8. 7Revision History

3.6 Dip Switches

There are three DIP switches S1, S2, and S3 on the back side of the PCB. S1 and S2 switches allow the user to disconnect the level shifter from the PMIC GPIOs or serial interfaces. The level shifter has pull-ups on the MCU side that can cause unwanted high state on the GPIO signals if configured in high impedance state. S3 switch is used for configuring chip select for target device in multi PMIC/stacked use case. See the Table 3-7 for the descriptions of the switches.

Table 3-7 Dip switches
Switch Pin Signal line
S1 1-16 SDA_I2C1/SDI_SPI
2-15 SCL_I2C1/SCK_SPI
3-14 SDA_I2C2/SDO_SPI
4-13 SCL_I2C2/CS_SPI
5-12 GPIO1
6-11 GPIO2
7-10 GPIO3
8-9 GPIO4
S2 1-16 GPIO5
2-15 GPIO6
3-14 GPIO7
4-13 GPIO8
5-12 GPIO9
6-11 GPIO10
7-10 Not connected
8-9 nINT
S3 1-12 CS5
2-11 CS4
3-10 CS3
4-9 CS2
5-8 CS1
6-7 GPIO2