SLVUC40
May 2021
TPS629210-Q1
Trademarks
1
Introduction
2
Performance Specification
3
EVM Configuration and Modification
3.1
Input and Output Capacitors
3.2
Configurable Enable Threshold Voltage
3.3
MODE/S-CONF Setting
3.4
Power Good
3.5
Power Good Pull Up Voltage
3.6
Feedforward Capacitor Option
3.7
Output Voltage Setting
3.8
Loop Response Measurement
4
EVM Test Set Up
4.1
Input and Output Connectors
4.2
Jumper Configuration
4.2.1
JP1 Enable
4.2.2
JP2 MODE/S-CONF
4.2.3
JP3 Power Good
4.2.4
JP4 PG Pull Up Voltage
5
Test Results
6
Board Layout
7
Schematic and Bill of Materials
7.1
Schematic
7.2
Bill of Materials
8
References
5
Test Results
This section provides the test results of TPS629210-Q1EVM.
Figure 5-1
Efficiency V
IN
= 12 V V
OUT
= 3.3 V F
SW
=2.5 MHz
Figure 5-2
Load Regulation V
IN
= 12 V V
OUT
= 3.3 V F
SW
=2.5 MHz
Figure 5-3
Line Regulation V
IN
= 5 V–17 V V
OUT
= 3.3 V I
OUT
= 0 A and 1 A
Figure 5-4
Loop Response Forced PWM Internal FB (VSET) V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 1 A
Figure 5-5
Output Voltage Ripple Auto PFM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 0 A
Figure 5-6
Output Voltage Ripple Forced PWM V
IN
= 12 V, V
OUT
= 3.3 V I
OUT
= 1 A
Figure 5-7
Input Voltage Ripple Forced PWM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 1 A
Figure 5-8
Enable Start Up Forced PWM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 1 A
Figure 5-9
Enable Shutdown Forced PWM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 1 A
Figure 5-10
Enable Pre-Bias Start Up Forced PWM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 0 A
Figure 5-11
Load Transient Response Forced PWM Internal FB (VSET) V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 0.5 A–1 A Slew Rate = 1 A/us
Figure 5-12
Thermal Performance Forced PWM V
IN
= 12 V V
OUT
= 3.3 V I
OUT
= 1 A F
SW
=2.5 MHz