SLVUC73B January   2022  – February 2024 TPS7H4003-SEP

 

  1.   1
  2.   TPS7H4003EVM Evaluation Module (EVM)
  3.   Trademarks
  4. 1TPS7H4003EVM Overview
    1. 1.1 Features
    2. 1.2 Applications
  5. 2TPS7H4003EVM Default Configuration
  6. 3TPS7H4003EVM Initial Setup
  7. 4TPS7H4003EVM Testing
    1. 4.1 Output Voltage Regulation
    2. 4.2 Output Voltage Ripple
    3. 4.3 Soft Startup
    4. 4.4 Transient Response to Positive and Negative Load Step (9A to 18A to 9A)
    5. 4.5 Loop Frequency Response
    6. 4.6 Setup
  8. 5TPS7H4003EVM Schematic
  9. 6TPS7H4003EVM Bill of Materials (BOM)
  10. 7Board Layout
  11. 8Support Resources
  12. 9Revision History

2 TPS7H4003EVM Default Configuration

Table 2-1 describes the default configuration of the TPS7H4003EVM listing the external components that define the converter design.

Table 2-1 Default EVM Configuration
PARAMETERSPECIFICATIONSDESCRIPTION
Input power supply5VBound by UVLO enable circuit (R9, R10)
Regulated output voltage1VR6 (RTOP) = 10kΩ, R7 (RBOTTOM) = 15.4kΩ
LOUT1.0µHChosen to meet inductor ripple current of 10% (Kind = 0.1)
COUT2mFChosen for (1) ESR = 1mΩ to set output voltage ripple; (2) value used during single event effects testing verify regulation maintained with single event upset to switching
Output current0A to 18ABy design
Switching frequency500kHzSet by R1 (RT) = 174kΩ
Soft start time constant≈2 msSet by C16 (Css) = 10nF
UVLO enable rising≈4.432 VSet by R10 = 10kΩ and R9 = 3.4kΩ
UVLO enable falling≈4.284 VSet by R10 = 10kΩ and R9 = 3.4kΩ
Loop bandwidth≈30 kHzSet by operational transconductance amplifier (OTA) compensation circuit: R4 (RCOMP) = 10kΩ, C17 (CCOMP) = 10nF, C18 (CHF) = 150pF
Loop phase margin≈60°
Gain margin≈–25 dB