SLVUCD2 January   2022 TPS65917-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2BOOT OTP Configuration
  4. 3Static Platform Settings
    1. 3.1 System Voltage Monitoring
    2. 3.2 SMPS
    3. 3.3 LDO
    4. 3.4 Interrupts
    5. 3.5 GPIO
    6. 3.6 MISC
    7. 3.7 SWOFF_HWRST
    8. 3.8 Shutdown_ColdReset
  5. 4Sequence Platform Settings
    1. 4.1 OFF2ACT Sequences
    2. 4.2 ACT2OFF Sequences

3.4 Interrupts

The interrupts are split into four register groups (INT1, INT2, INT3, and INT4). All interrupts are logically combined on a single output line, INT (default active-low). This line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the device. The OTP settings in this section show whether each interrupt is enabled or disabled by default.

Table 3-4 INT1 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
INT1_MASKVSYS_MONEnable and disable interrupt from the VSYS_MON comparator1: Interrupt generation disabled
PWRDOWNEnable and disable interrupt from the PWRDOWN pin1: Interrupt generation disabled
PWRONEnable and disable interrupt from PWRON pin. A PWRON event is always an ON request.1: Interrupt generation disabled
LONG_PRESS_KEYEnable and disable interrupt from long key press on the PWRON pin1: Interrupt generation disabled
HOTDIEEnable and disable interrupt from device hot-die detection. The interrupt can be used as a pre-warning for processor to limit the PMIC load, before increasing die temperature forces shutdown.0: Interrupt generated
Table 3-5 INT2 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
INT2_MASKSHORTTriggered from internal event of SMPS or LDO outputs failing. If an interrupt is enabled, it is an ON request.0: Interrupt generated
WDTEnable and disable interrupt from watchdog expiration1: Interrupt generation disabled
FSDEnable and disable First Supply Detection (FSD) interrupt1: Interrupt generation disabled
RESET_INEnable and disable interrupt from the RESET_IN pin1: Interrupt generated disabled
Table 3-6 INT3 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
INT3_MASKVBUSInterrupt to detect rising or falling VBUS line1: Interrupt generation disabled
GPADC_EOC_SWGPADC result ready from software-initiated conversion1: Interrupt generation disabled
GPADC_AUTO_1GPADC automatic conversion result 1 above or below the reference threshold1: Interrupt generation disabled
GPADC_AUTO_0GPADC automatic conversion result 0 above or below the reference threshold1: Interrupt generation disabled
Table 3-7 INT4 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
INT4_MASKGPIO_6Enable and disable interrupt from the GPIO6 pin rising or falling edge1: Interrupt generation disabled
GPIO_5Enable and disable interrupt from the GPIO5 pin rising or falling edge1: Interrupt generation disabled
GPIO_4Enable and disable interrupt from the GPIO4 pin rising or falling edge1: Interrupt generation disabled
GPIO_3Enable and disable interrupt from the GPIO3 pin rising or falling edge1: Interrupt generation disabled
GPIO_2Enable and disable interrupt from the GPIO2 pin rising or falling edge1: Interrupt generation disabled
GPIO_1Enable and disable interrupt from the GPIO1 pin rising or falling edge1: Interrupt generation disabled
GPIO_0Enable and disable interrupt from the GPIO0 pin rising or falling edge1: Interrupt generation disabled