SLVUCF3 March   2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , LP8764-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

7.1 Initialization

After initial power up the first two actions are to remap the SOC power triggers to the MCU power error and service (clear) the interrupts.

The default mapping of the SOC Rail trigger in both PMICs is the SOC Power error. In this PDN, the SOC Power error and the associated SOC power error sequence put the PMICs and the processor in a non-functional state. To avoid any SOC power error from causing a transition to this non-functional state, the mapping must be changed to the MCU Power error. The following instructions change the mapping:


Write 0x48:0x44:0x08:0xF3    //  SOC_RAIL_TRIG = MCU Power Error (10b) 
Write 0x4C:0x44:0x08:0xF3    //  SOC_RAIL_TRIG = MCU Power Error (10b)

Upon a successful power up, the BIST_PASS_INT and ENABLE_INT interrupts are set. Any other interrupts indicate an issue but the automated recovery attempt was successful. The recommended procedure is to:

  1. Interrogate the interrupts
  2. Determine the course of action
  3. Set the NSLEEP bits
  4. Clear the interrupts
The following example assumes that there are no interrupts other than the BIST_PASS_INT and ENABLE_INT after power up and the enable pin goes high.

Read  0x48:0x5A              // Read INT_TOP to determine errors
Read  0x48:0x65              // Read the STARTUP_INT register
Read  0x48:0x66              // Read the MISC_INT register
Write 0x48:0x86:0x03:0xFC    // Set NSLEEP1 and NSLEEP2 in TPS65951213
Write 0x48:0x66:0x01:0xFE    // Clear BIST_PASS_INT
Write 0x48:0x65:0x26:0xD9    // Clear all potential sources of the On Request