SLVUCG9 October   2022 TPS36-Q1

 

  1.   Abstract
  2. 1Trademarks
  3. 2Introduction
    1. 2.1 Related Documentation
  4. 3Schematic, Bill of Materials, and Layout
    1. 3.1 TPS36Q1EVM Schematic
    2. 3.2 TPS36Q1EVM Bill of Materials
    3. 3.3 Layout and Component Placement
  5. 4EVM Connectors
    1. 4.1 EVM Jumpers
    2. 4.2 EVM Test Points
  6. 5EVM Setup and Operation
    1. 5.1 Input Power (VDD)
    2. 5.2 RESET
    3. 5.3 Manual Reset (MR)
    4. 5.4 SET0 and SET1
    5. 5.5 Watchdog Enable (WD_EN)
    6. 5.6 Watchdog Input (WDI)
    7. 5.7 Watchdog Output (WDO)
    8. 5.8 CRST
    9. 5.9 CWD
  7. 6EVM Performance Results
  8. 7Revision History

5.9 CWD

A capacitor between the CWD pin and GND sets the watchdog timeout period tWD for TPS35-Q1 and TPS3435-Q1 devices or the watchdog close window period tWC for TPS36-Q1 and TPS3436-Q1 devices. The TPS36Q1EVM offers two pre-installed options: 0.01µF and 1µ. These capacitors correspond to 49.5ms and 4.95s tWD time delays for the TPS35-Q1 and TPS3435-Q1 devices, respectively. The tWD values are determined by the SET0 and SET1 pins; please refer to Table 5-1 for a list of the values and the data sheet for the tWD calculation. Refer to Table 4-1 and Table 4-2 for suggested jumper settings. If other timing option is needed, the capacitor can be replaced. Refer to the respective device data sheet to determine the capacitor value for required timing.

Table 5-1 Typical tWC Values for TPS36-Q1 and TPS3436-Q1

SET0

SET1

0.01µF

1µF

0

0

0.792s

79.2s

0

1

0.396s

39.6s

1

0

Disabled/"00" if using Pinouts C or D

1

1

0.099s

9.9s