SLVUCI2 march   2023 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TPS6594-Q1

 

  1.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  2.   Trademarks
  3. 1Introduction
  4. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  5. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  6. 4Static NVM Settings.
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  7. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  8. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  9. 7References

4.7 Finite State Machine (FSM) Settings

These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup.

Table 4-7 FSM NVM Settings
Register Name Field Name TPS6594
Value Description
RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group
BUCK2_GRP_SEL 0x1 MCU rail group
BUCK3_GRP_SEL 0x2 SOC rail group
BUCK4_GRP_SEL 0x2 SOC rail group
RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group
LDO1_GRP_SEL 0x1 MCU rail group
LDO2_GRP_SEL 0x1 MCU rail group
LDO3_GRP_SEL 0x2 SOC rail group
RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group
VCCA_GRP_SEL 0x1 MCU rail group
FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x2 MCU power error
SOC_RAIL_TRIG 0x2 MCU power error
OTHER_RAIL_TRIG 0x1 Orderly shutdown
SEVERE_ERR_TRIG 0x0 Immediate shutdown
FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown