In the event of an error on any of the power rails which are part of the MAIN/SOC power rail group, the PWR_SOC_ERROR sequence is performed. The nRSTOUT_SOC pin is pulled low and the SOC power rails execute a normal processor power down sequence except the MCU power group remains energized as shown in Figure 5-6. The state of the I2C_7 trigger in the PMIC determines whether the DDR supplies and control signals remain energized (I2C_7=1) or disabled (I2C_7=0), as shown in Figure 5-7.

In the start of the sequence the following instructions are executed:

// TPS6594133A
// Set AMUXOUT_EN and CLKMON_EN, clear LPM_EN and nRSTOUT_SOC
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE1
// Clear SPMI_LPM_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF

Figure 5-6 PWR_SOC_ERROR with I2C_7 High

Figure 5-7 PWR_SOC_ERROR with I2C_7 Low