SLVUCI2 User guide

SLVUCI2 march 2023 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TPS6594-Q1

5.2 PFSM Triggers

As shown in Figure 5-1, there are various triggers that can enable a state transition between configured states. Table 5-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated sequence.

Table 5-1 State Transition Triggers

Trigger	Priority (ID)	Immediate (IMM)	REENTERANT	PFSM Current State	PFSM Destination State	Power Sequence or Function Executed
Immediate Shutdown⁽⁷⁾	0	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾	TO_SAFE_SEVERE
MCU Power Error	1	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾	TO_SAFE_ORDERLY
GPIO10 Low	2	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾
Orderly Shutdown⁽⁷⁾	3	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾
OFF Request	5⁽⁹⁾	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	STANDBY⁽²⁾	TO_STANDBY
WDOG Error	6	False	True	ACTIVE	ACTIVE	ACTIVE_TO_WARM
ESM MCU Error	7	False	True	ACTIVE	ACTIVE	ACTIVE_TO_WARM
ESM SOC Error	8	False	True	ACTIVE	ACTIVE	ESM_SOC_ERROR
WDOG Error	9	False	True	MCU ONLY	MCU ONLY	MCU_TO_WARM
ESM MCU Error	10	False	True	MCU ONLY	MCU ONLY	MCU_TO_WARM
SOC Power Error	11	False	False	ACTIVE	MCU ONLY	PWR_SOC_ERR
GPIO8 Low	12	False	False	ACTIVE	MCU ONLY	PWR_SOC_ERR
I2C_1 bit is high⁽³⁾	13	False	True	ACTIVE, MCU ONLY	No State Change	Execute RUNTIME BIST
I2C_2 bit is high⁽³⁾	14	False	True	ACTIVE, MCU ONLY	No State Change	Enable I²C CRC on I²C1 and I²C2.⁽⁴⁾
ON Request	15	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE	TO_ACTIVE
WKUP1 goes high	16	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE
NSLEEP1 and NSLEEP2 are high⁽⁵⁾	17	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE
MCU ON Request	18	False	False	STANDBY, ACTIVE⁽⁶⁾, MCU ONLY, Suspend-to-RAM	MCU ONLY	TO_MCU
WKUP2 goes high	19	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	MCU ONLY
NSLEEP1 goes low and NSLEEP2 goes high⁽⁵⁾	20	False	False	ACTIVE, MCU ONLY, Suspend-to-RAM	MCU ONLY
NSLEEP1 goes low and NSLEEP2 goes low⁽⁵⁾	21	False	False	ACTIVE, MCU ONLY	Suspend-to-RAM	TO_RETENTION
NSLEEP1 goes high and NSLEEP2 goes low⁽⁵⁾	22	False	False	ACTIVE, MCU ONLY	Suspend-to-RAM	TO_RETENTION
I2C_0 bit goes high⁽³⁾	23⁽⁸⁾	False	False	STANDBY, ACTIVE, MCU ONLY	LP_STANDBY⁽²⁾	TO_STANDBY

(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in Table 4-10). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.

(2) If the LP_STANDBY_SEL bit is set in the TPS6594133A-Q1 (see RTC_CTRL_2, in Table 4-10), then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY. Refer to the data sheet for more details.

(3) I2C_0, I2C_1, and I2C_2 are self-clearing triggers.

(4) Enabling the I²C CRC, enables the CRC on both I2C1 and I2C2, however, the I2C2 is disabled for 2ms after the CRC is enabled. Be aware when using the watchdog Q&A before enabling I²C CRC. The recommendation is to enable the I²C CRC first, and then after 2ms, start the watchdog Q&A.

(5) NSLEEP1 and NSLEEP2 of the PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.

(6) When in the ACTIVE mode, the ON Request to MCU ONLY trigger cannot be accessed while other higher priority triggers, like NSLEEP1=NSLEEP2=HIGH, are still active.

(7) These triggers can originate from the TPS6594133A.

(8) Trigger ID 23 not available until the NSLEEP bits are masked: NSLEEP2_MASK=NSLEEP1_MASK=1.

(9) Trigger IDs 4, 24, and 25 (not shown) are enabled and activated by the power sequences. These triggers are used to manage the transition between the PFSM and the FSM.