#FIG_XHW_CCV_HVB shows the power mapping between the dual TPS6594-Q1 PMIC and LP8764-Q1 PMIC power resources and processor voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

For SD card dual-voltage I/O support (3.3 V and 1.8 V), the TLV7103318-Q1 device can be used. A processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. The GPIO allows control of the TLV7103318-Q1 voltage without the need for the MCU processor to establish I2C communication with the PMICs during boot from SD card operations.

This PDN uses six discrete power components with three being required and three are optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused feedback pin, FB_B3, of the TPS65941120-Q1 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_MCUIO_3V3_LS power rail. The unused feedback pin, FB_B4 of the LP876411B5-Q1 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_IO_3V3 power rail. The FB_B4 feedback pin enables all of the necessary processor power supply inputs to have voltage monitoring coverage as needed for functional safety ASIL-B and higher systems. The third discrete device is a TLV73318P-Q1 LDO which supplies the LPDDR4 SDRAM component with required 1.8V supply, which is monitored by the unused feedback pin, FB_B3, of the LP876411B5-Q1. The fourth discrete power component is an optional TLV73333-Q1 LDO that can be used for USB support. The fifth discrete power component is an optional TLV77103318-Q1 LDO for SD power. The sixth discrete component is TLV73318P-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.

• * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
• ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD.

Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there are additional options for including or excluding the VPP_x(EFUSE) rail, the SD CARD rail, and the USB rail.