SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

5.12 Multi-Device Settings

These settings detail whether the device is a operating as a primary or secondary in the system. These settings cannot be changed after device startup.

Table 5-12 Multi-Device NVM Settings
Register Name Field Name TPS65941120-Q1 TPS65941421-Q1 LP876411B5-Q1
Value Description Value Description Value Description
SPMI_CONFIG_1 SPMI_CRC_EN 0x1 SPMI CRC check enabled 0x1 SPMI CRC check enabled 0x1 SPMI CRC check enabled
BIT 1 0x1 Controller mode 0x0 Secondary mode 0x0 Secondary mode
SPMI_CLK_SEL 0x2 5MHz 0x2 5MHz 0x2 5MHz
SPMI_CONFIG_2 SPMI_IF_SEL 0x0 Debug feature and uses controller logic to implement logical secondary. 0x0 Debug feature and uses controller logic to implement logical secondary. 0x0 Debug feature and uses controller logic to implement logical secondary.
SPMI_RETRY_LIMIT 0x3 Three retries in case of error detected 0x3 Three retries in case of error detected 0x3 Three retries in case of error detected
SPMI_WD_AUTO_BOOT 0x1 SPMI auto boot enabled 0x1 SPMI auto boot enabled 0x1 SPMI auto boot enabled
SPMI_EN 0x1 SPMI enabled 0x1 SPMI enabled 0x1 SPMI enabled
SPMI_WD_EN 0x1 SPMI WD enabled 0x1 SPMI WD enabled 0x1 SPMI WD enabled
SPMI_CONFIG_3 SPMI_WD_BOOT_ INTERVAL 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_WD_RUNTIME_ INTERVAL 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_CONFIG_4 SPMI_WD_RESPONSE_ TIMEOUT 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_PFSM_RESPONSE_ TIMEOUT 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_CONFIG_5 SPMI_WD_RUNTIME_BIST_ TIMEOUT 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_WD_BOOT_BIST_ TIMEOUT 0x8 0x8 0x8 0x8 0x8 0x8
SPMI_CONFIG_6 BOOT_DELAY 0x0 0x0 0x0 0x0 0x0 0x0
SPMI_ID SPMI_SID 0x5 0x5 0x3 0x3 0xc 0xc
SPMI_MID 0x0 0x0 0x0 0x0 0x0 0x0