SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

6.1 Configured States

In this PDN, the PMIC devices have the following four configured power states:

  • Standby
  • Active
  • MCU Only
  • Pwr SoC Error
  • Retention

In #GUID-DDB7BBE6-2B0A-442C-97FB-917ADEF20883, the configured PDN power states are shown, along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6594-Q1 and LP8764-Q1 data sheets, see GUID-CA8B39C1-D169-4AD7-A6CF-FEFEF4060510.html.

Figure 6-1 Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions

When the PMICs transition from the FSM to the PFSM, several initialization instructions are performed to disable the residual voltage checks on both the BUCK and LDO regulators. Additionally, the FIRST_STARTUP_DONE bit is set and VCCA OV and UV masks are cleared (which are set in the static configurations, Table 5-8). After these instructions are executed the PMICs wait for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below:

    RetentionThe PMICs are powered by a valid supply. When the PMICs I2C_7 triggers are set (DDR Retention), 2 SoC voltage domains (vdds_ddr_bias and vdds_ddr) remain energized, in addition to the LPDDR4, while all other domains are off to minimize total system power. When the PMICs I2C_5 triggers are set (GPIO Retention), 4 voltage domains (vdd_mcu_wake1, vddshv0_mcu, vdd_wake0, vddshv2) remain energized, while all other domains are off to minimize total system power. EN_DRV is forced low in this state. Refer to the GUID-5B8BB447-89E7-41CE-B027-EFCDDF7D4CBA.html#GUID-5B8BB447-89E7-41CE-B027-EFCDDF7D4CBA sequence description.