SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

3.2 Control Mapping

#FIG_LMF_QHH_MQB shows the digital control signal mapping between processor and PMIC devices. For the three PMIC devices to work together, the PMICs must establish an SPMI communication channel. The SPMI allows the two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the TPS6594-Q1 and the GPIO_8 and GPIO_9 pins of the LP8764-Q1 are assigned for this functionality.

Other digital connections from the PMICs to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

The digital connections shown in TPS6594-Q1 Digital Connections allow system features including 'MCU-only, MCU Safety Island' and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation.

Figure 3-2 PDN-0A Digital Connections
  1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the device data sheet for a complete description. The PMIC voltage domains indicated are for the PDN-0A NVM configuration.
  2. WKUP2 triggers a transition to MCU Only state. LP_WKUP1 and WKUP1 transition to the ACTIVE state GUID-5B640415-4214-468F-8BC9-89BCA48A5DDE.html#GUID-DDB7BBE6-2B0A-442C-97FB-917ADEF20883
Note: The PMIC voltage domain of an IO can be different depending upon configuration. When configured as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and GPIO4 are in the VINT domain.
Note: In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2 Open-drain signals and Power Rail
PDN SignalPullup Power Rail
H_MCU_INTnVDD_MCUIO_1V8
H_MCU_PORz_1V8VDA_MCU_1V8
H_SOC_PORz_1V8VDA_MCU_1V8
H_DDR_RET_1V1VDD_DDR_1V1_REG
H_WKUP_I2C0VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDAVDD_MCUIO_3V3

Please use Table 3-3as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. GPIO reconfiguration is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). For details on how functional safety related connections help achieve functional safety system-level goals, see GUID-D64CCBD4-435C-4C7C-9EB8-FB4BA8232AB5.html.

Table 3-3 Digital Connections by System Feature
Device GPIO Mapping System Features#GUID-D482FDF0-0588-4DAA-B617-A3C252ADE3C1
PMIC Pin NVM Function PDN Signals Active SoC Functional Safety MCU - only MCU-Safety Island GPIO Retention DDR Retention SD Card
TPS65941120-Q1 nPWRON/ ENABLE Enable SOC_PWR_ON R
INT INT H_MCU_INTn R
nRSTOUT nRSTOUT H_MCU_PORz_1V8 R R
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R
SDA_I2C1 SDA_I2C1 H_WKUP_I2C0 R
GPIO_1 SCL_I2C2 H_MCU_I2C0_SCL R
GPIO_2 SDA_I2C2 H_MCU_I2C0_SDA R
GPIO_3 nERR_SoC H_SOC_SAFETY_ERRn R
GPIO_4 LP_WKUP1#GUID-4B5F6C6A-A20C-4D57-9EE1-A30FEB46D006 PMIC_FULL_ACTIVEn R R
GPIO_5 SCLK_SPMI PMICA_SCLK R
GPIO_6 SDATA_SPMI PMICA_SDATA R
GPIO_7 nERR_MCU H_MCU_SAFETY_ERRn R
GPIO_8 DISABLE_WDOG PMICA_GPIO8 #GUID-6AC13799-EDB9-4F36-A043-A4C0EC83013D #GUID-6AC13799-EDB9-4F36-A043-A4C0EC83013D
GPIO_9 GPO EN_MCU3V3IO R R
GPIO_10 WKUP1 PMICA_GPIO10/ H_PMIC_PWR_EN1 O
GPIO_11 nRSTOUT_SOC H_SOC_PORz_1V8 R
TPS65941421-Q1 nPWRON/ENABLE ENABLE Unused
nINT nINT H_MCU_INTn
nRSTOUT nRSTOUT Unused
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R
SDA_I2C1 SCL_I2C1 H_WKUP_I2C0 R
GPIO_1 GPO Unused#GUID-7845E0FD-DEE5-4204-9569-1DC02F1404BE
GPIO_2 GPI Unused#GUID-F1CADDC3-64C6-496A-B855-05A9EEDD09C8 R
GPIO_3 GPO EN_DDR_VDD1 R O R
GPIO_4 GPO H_DDR_RET_1V1 R
GPIO_5 SCLK_SPMI PMICB_SCLK R
GPIO_6 SDATA_SPMI PMICB_SDATA R
GPIO_7 GPI Unused#GUID-7845E0FD-DEE5-4204-9569-1DC02F1404BE
GPIO_8 GPI Unused#GUID-7845E0FD-DEE5-4204-9569-1DC02F1404BE
GPIO_9 GPO EN_EFUSE_LDO#GUID-7845E0FD-DEE5-4204-9569-1DC02F1404BE
GPIO_10 WKUP2 WK_MCU_ONLYn#GUID-7845E0FD-DEE5-4204-9569-1DC02F1404BE O
GPIO_11 GPO EN_3V3IO R
LP876411B5-Q1 nINT nINT H_MCU_INTn R
nRSTOUT nRSTOUT Unused
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R
SDATA_I2C1 SDATA_I2C1 H_WKUP_I2C0 R
GPIO_1 GPIO_1 Unused
GPIO_2 GPIO_2 Unused
GPIO_3 GPIO_3 Unused
GPIO_4 GPIO_4 Unused
GPIO_5 GPIO_5 Unused
GPIO_6 GPIO_6 Unused
GPIO_7 GPIO_7 Unused
GPIO_8 SCLK_SPMI PMICC_SCLK R
GPIO_9 SDATA_SPMI PMICC_SDATA R
GPIO_10 GPIO_10 Unused
(1) R is Required. O is optional.
(3) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(4) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if desired.
(5) GPIO4 of the TPS65941111 is not part of the power sequences, GUID-C4EB5B6E-C9E2-46E0-B5A5-085D4EE72490.html#GUID-C4EB5B6E-C9E2-46E0-B5A5-085D4EE72490. This GPIO must be configured by the SOC at runtime.