SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

4.2 Achieving up to ASIL-D System Requirements

For ASIL-C or ASIL-D systems, the following features in addition to the ones described in GUID-A7785222-D284-46BA-B230-451D521837E5.html#GUID-A7785222-D284-46BA-B230-451D521837E5 can be used:

  • PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
  • PMIC current monitoring on all output power rails
  • SoC error monitoring
  • Switch short-to-ground detection on BUCK regulator pins (SW_Bx)
  • Residual Voltage Monitoring
  • Read-back of Logic Output Pins
    • nINT of all PMICs
    • nRSTOUT and nRSTOUT_SOC of the primary PMIC

The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 and LP8764-Q1 devices.

GPIO_3 of the primary TPS6594-Q1 PMIC is configured as the SoC error signal monitor. Similar to the MCU error signal monitor, this feature is enabled through I2C using the ESM_SOC_EN register bit. The SoC reset functionality is supported through the connection of GPIO_11 on the primary TPS6594-Q1, configured as nRSTOUT_SoC, to the PORz pin of the processor.

Table 4-1 System Level Safety Features
ASIL-BASIL-D
Safety Monitoring ProcessorExternal SW Wdog INTn

Safety MCU Processing ESM

Safety MCU Reset

Safety Status Signal with IO Read-Back featureSystem Input Voltage Monitoring

SoC Main Processing ESM

IO Read-Back Feature

SoC: MCU Island

R5 Cores

PMICA: Q&A Watchdog and I2C2

PMICA(1) and PMICB(2) : nINT

PMICA: nERR_MCU connected to SOC:MCU_SAFETY_ERRz

PMICA: nRSTOUT connected to MCU_PORz_1V8

PMICA: ENDRVPMICA: VSYS_SENSE -OV with Safety FET OVPGDRV

PMICA, PMICB and PMICC with VCCA OV & UV and SoC (VMON1) -UV

PMICA: nERR_SoC connected to SOC: SOC_SAFETY_ERRz

PMICA: nINT, nRSTOUT, nRSTOUT_SOC

PMICB: nINT

PMICC: nINT

(1) PMICA = TPS65941120-Q1
(2) PMICB = TPS65941421-Q1
Table 4-2 Power Monitoring Safety Features
ASIL-BASIL-D Adds
DevicePower ResourcePDN Power RailSafe State Power Group(1)Supply Voltage MonitoringSupply Current MonitoringResidual Voltage Monitoring
TPS65941120-Q1 (PMIC-A)BUCK1-4VDD_CPU_AVSSOCPMIC-A - OV & UVPMIC-A -CMPMIC-A -RVM
BUCK5VDD_MCU_0V85MCUPMIC-A - OV & UVPMIC-A -CMPMIC-A -RVM
LDO1VDD_MCUWK_0V8MCUPMIC-A - OV & UVPMIC-A -CM (2)PMIC-A -RVM(2)
LDO2VDD_MCU_GPIORET_3V3MCUPMIC-A - OV & UVPMIC-A -CMPMIC-A -RVM
LDO3VDD_MCUIO_1V8MCUPMIC-A - OV & UVPMIC-A -CMPMIC-A -RVM
LDO4VDA_MCU_1V8MCUPMIC-A - OV & UVPMIC-A -CMPMIC-A -RVM
TPS65941421-Q1 (PMIC-B)BUCK1VDD_IO_1V8SOCPMIC-B - OV & UVPMIC-B -CMPMIC-B -RVM
BUCK3 VDD_PHY_1V8 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
BUCK4 VDD_DDR_1V1 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
BUCK5 VDD_RAM_0V85 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
LDO1 VDD_WK_0V8 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
LDO2 VDD_GPIORET_3V3 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
LDO3 VDA_DLL_0V8 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
LDO4 VDA_PLL_1V8 SOC PMIC-B - OV & UV PMIC-B -CM PMIC-B -RVM
LP876411B5-Q1 BUCK1-4 VDD_CORE_0V8 SOC PMIC-C - OV & UV PMIC-C -CM PMIC-C -RVM
TPS22965-Q1Ld Sw AVDD_MCUIO_3V3MCUPMIC-A (FB_B3) - OV & UV(5)NA(3)(4)
TPS22965-Q1 Ld Sw B VDD_IO_3V3 SOC PMIC-C (FB_B4) - OV & UV(5) NA(3)(4)
TLV3318P-Q1LDO-AVDD1_DDR_1V8SOCPMIC-C (FB_B3) -OV & UV(5)NA
TLV7103318-Q1LDO-BVDD_SD_DVNoneNA(2)NA(2)
TLV73333P-Q1LDO-CVDDA_3P3_USBNoneNA(2)NA(2)
TLV73318P-Q1LDO-DVDD_EFUSE_1V8NoneNA(2)NA(2)
(1) Rail Group settings for the TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 are found in Table 5-7.
(2) Power rails VDDSHV5, VPP_CORE, VPP_MCU, VDDA_3P3_USB, and VDD1_LPDDR4_1V8 are not safety critical.
(3) Power rails VDD_IO_1V8/3V3 are typically not safety critical since other means are available (for example, black-channel checkers) to provide diagnostic coverage to detect faults in SoC signaling interfaces (for example, CAN, UART, and SPI).
(4) If an SoC GPIO control signal is used in a safety critical interface, then adding voltage and current monitoring to specific VIO power rail may be needed per customer's end product design.
(5) PMIC-C, Buck3 and 4 have unused remote sense feedback inputs that can be assigned to provide OV and UV voltage monitoring after SoC SW boot for 2x external power rails per desired functional safety needs. Optional OV/UV monitoring of VDD_DDR_1V1 and VDD_IO_3V3 power rails are examples.