SLVUCK2A january   2023  – april 2023 TPS7H3302-SEP

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Description
    1. 2.1 Related Information
    2. 2.2 Typical Applications
    3. 2.3 Features
    4. 2.4 Performance Specification Summary
  5. 3Test Setup
    1. 3.1 Equipment
      1. 3.1.1 Power Supplies
      2. 3.1.2 Load #1
    2. 3.2 EVM Connectors and Test Points
    3. 3.3 Testing Procedure
      1. 3.3.1 EVM Bode Plot Measurement Setup
      2. 3.3.2 EVM Transient Test
  6. 4Board Layout
  7. 5Schematic
  8. 6Bill of Materials
  9. 7Related Documentation
  10. 8Revision History

3.3.1 EVM Bode Plot Measurement Setup

The setup for EVM bode plot measurement is as follows:

  1. Use a Bode 100 loop analyzer or equivalent equipment.
  2. Remove jumper on J5 to isolate VDDQSNS from VLDOIN. To test with VLDOIN tied to single VDDQ along with VDDQSNS, use the optional filter. See note below.
  3. Connect the oscillator output across R3 = 51 Ω resistor. Connect the output of oscillator to TP4 (VTTSNS).
  4. Connect Channel 2 of the analyzer at TP5 and connect ground to TP2
  5. Connect Channel 1 of the analyzer at TP4 and connect ground to TP2.
  6. Power EVM with desired conditions for VLDOIN, VIN, VDDQSNS, and VTT load.
  7. With the EVM loaded to the required load, run bode plot over desired frequency range.

To verify stability across loads and rated operating temperature, implement a quantity of four 4.7 uF ceramic output capacitors in the application circuit.

Attention: All of the bode measurements presented, VDDQSNS is provided from an independent supply from VLDOIN. If VDDQSNS and VLDOIN inputs are connected to same supply, then use the isolation filter on the EVM to isolate the load effects on VLDOIN from VDDQSNS. The filter can be used by replacing components for R4, and C3.
Figure 3-1 through Figure 3-3 show bode plots for this EVM. All plots generated using default CIN and COUT capacitances populated on EVM. CIN = 150 µF tantalum // 5-10 µF ceramic, COUT = 3-150 µF tantalum // 4-4.7 µF ceramic.

GUID-20230414-SS0I-TM92-LHBF-X5PCG1NMC0WJ-low.svg Figure 3-1 DDR3 Bode Plot Iload = 500 mA
GUID-20230414-SS0I-GW1X-9Q2Q-BRCHGMW87ZWM-low.svg Figure 3-2 DDR3 Bode Plot Iload = 1 A
GUID-20230414-SS0I-5THT-SMLG-CNZHR8JHH2XW-low.svg Figure 3-3 DDR3 Bode Plot Iload = 3 A

TI recommends that VLDOIN and VDDQSNS be isolated from each other. If isolating VLDOIN and VDDQSNS is not possible, then add an external input filter between VLDOIN and VDDQSNS. Adding an RC filter between VLDOIN and VDDQSNS results in some loss of dynamic tracking of VTT and VTTREF to VDDQSNS.