SLVUCK4A march 2023 – july 2023 TPS25948
Table 4-1 lists the TPS25948EVM eFuse evaluation board input and output connector functionality. Table 4-2 and Table 4-3 describe the test point availability and the jumper functionality. Table 4-4 describes the function of signal LEDs.
Channel | Connector | Label | Description |
---|---|---|---|
CH1 | J2 | VIN1(+), PGND(–) | Input of CH1 |
J1 | VOUT1(+), PGND(–) | Output of CH1 | |
CH2 | J12 | VIN2(+), PGND(–) | Input of CH2 |
J11 | VOUT2(+), PGND(–) | Output of CH2 |
Channel | Test Points | Label | Description |
---|---|---|---|
CH1 | TP1 | VIN1 | CH1 input voltage |
TP2 | VOUT1 | CH1 output voltage | |
TP4 | EN/UVLO1 | CH1 EN/UVLO signal | |
TP5 | OVLO1 | CH1 OVLO signal | |
TP6 | ITIMER1 | CH1 ITIMER signal | |
TP7 | dVdt1 | CH1 output voltage ramp control | |
TP8 | ILM1 | CH1 current limit and monitor signal | |
TP10 | FLTb1 | CH1 fault signal | |
TP9 | SPLYGD1 | CH1 supply good signal | |
TP13 | GND1 | CH1 IC GND signal | |
CH2 | TP14 | VIN2 | CH2 input voltage |
TP15 | VOUT2 | CH2 output voltage | |
TP16 | EN/UVLO2 | CH2 EN/UVLO signal | |
TP17 | OVLO2 | CH2 OVLO signal | |
TP18 | ITIMER2 | CH2 ITIMER signal | |
TP19 | dVdt2 | CH2 output voltage ramp control | |
TP20 | ILM2 | CH2 current limit and monitor signal | |
TP22 | RCBCTRL2 | CH2 reverse current blocking control signal | |
TP21 | SPLYGD2 | CH2 supply good signal | |
TP25 | GND2 | CH2 IC GND signal | |
CH1 & CH2 | TP3 | VCC_EXT | External VCC voltage point for CH1 and CH2 |
TP11,TP12,TP23,TP24 | PGND | Common Power GND for CH1 and CH1 |
Channel | Jumper | Label | Description | Default Jumper Position |
---|---|---|---|---|
CH1 | J5 | dVdt1 | 1-2 position sets the output slew rate to 1.5 mV/us | 3-4 |
3-4 position sets the output slew rate to 0.5 mV/us | ||||
5-6 position sets the output slew rate to 0.23 mV/us | ||||
J6 | ILM1 | 1-2 position sets the current limit to 1 A | 7-8 | |
3-4 position sets the current limit to 3 A | ||||
5-6 position sets the current limit to 4.5 A | ||||
7-8 position sets the current limit to 9 A | ||||
J8 | ITIMER1 | 1-2 position sets the transient current blanking period to 170 us | 3-4 | |
3-4 position sets the transient current blanking period to 1.7 ms | ||||
5-6 position sets the transient current blanking period to 17 ms | ||||
J7 | OVLO1 | 1-2 position sets input OVLO threshold at 13.8 V | 3-4 | |
3-4 position sets input OVLO threshold at 16.4 V | ||||
5-6 position sets input OVLO threshold at 21.5 V | ||||
J4 | OVLO1_VIN1 | Connects OVLO pin to VIN resistor ladder | 1-2 | |
J3 | UVLO1_VIN1 | Connects UVLO pin to VIN resistor ladder | 1-2 | |
J15 | dVdt2 | 1-2 position sets the output slew rate to 1.5 mV/us | 3-4 | |
3-4 position sets the output slew rate to 0.5 mV/us | ||||
5-6 position sets the output slew rate to 0.23 mV/us | ||||
J16 | ILM2 | 1-2 position sets the current limit to 1 A | 7-8 | |
3-4 position sets the current limit to 3 A | ||||
5-6 position sets the current limit to 4.5 A | ||||
CH2 | 7-8 position sets the current limit to 9 A | |||
J19 | ITIMER2 | 1-2 position sets the transient current blanking period to 170 us | 3-4 | |
3-4 position sets the transient current blanking period to 1.7 ms | ||||
5-6 position sets the transient current blanking period to 17 ms | ||||
J18 | OVLO2 | 1-2 position sets input OVLO threshold at 13.8 V | 3-4 | |
3-4 position sets input OVLO threshold at 16.4 V | ||||
5-6 position sets input OVLO threshold at 21.5 V | ||||
J20 | OVLO2_SPLYGD1 | 1-2 Position connects the SPLYGD1 with OVLO2. Use this setting for Power Muxing operation of U1 and U2 | 2-3 | |
2-3 position connects OVLO2 to VIN resistor ladder | ||||
J21 | UVLO2_SPLYGD1 | 1-2 Position connects the SPLYGD1 with EN/UVLO2. Use this setting for parallel operation of U1 and U2 | 2-3 | |
2-3 position connects EN/UVLO2 to VIN resistor ladder | ||||
J14 | OVLO2_VIN2 | Connects OVLO pin to VIN resistor ladder | 1-2 | |
J13 | UVLO2_VIN2 | Connects UVLO pin to VIN resistor ladder | 1-2 | |
J17 | RCBCTRL2 | Connects RCBCTRL to GND to disable reverse current blocking | Open | |
CH1 & CH2 | J9 | VCC connection CH-1,2 | 2-3 position connects onboard generated voltage, VCC as reference for digital signals of U1 and U2 | 2-3 |
LED | Description |
---|---|
D1 | When ON, indicates that SPLYGD is asserted for channel 1 |
D3 | When ON, indicates that FLTb is asserted for channel 1 |
D7 | When ON, indicates that SPLYGD is asserted for channel 2 |