SLVUCM2A january   2023  – july 2023 TPSF12C3 , TPSF12C3-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
      1. 2.2.1 High-Voltage Testing
      2. 2.2.2 EVM Connections
      3. 2.2.3 Low-Voltage Testing
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Insertion Loss
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.2.1 High-Voltage Testing

Referencing the header connections described in Table 3-1, use the recommended setup from the schematic of Figure 3-3 to evaluate the performance of the TPSF12C3 with a three-phase AC/DC regulator.

GUID-20221101-SS0I-RM8N-QDVW-2M8JFKGMPGCG-low.svg Figure 2-2 EVM Setup Schematic for High-Voltage Testing With a Three-Phase AC/DC Regulator