SLVUCM2A january   2023  – july 2023 TPSF12C3 , TPSF12C3-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
      1. 2.2.1 High-Voltage Testing
      2. 2.2.2 EVM Connections
      3. 2.2.3 Low-Voltage Testing
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Insertion Loss
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.3 Header Information

As outlined in Table 3-1, header J1 provides connections to the low-voltage side of the SENSE capacitors (corresponding to the SENSE pins of the IC), the low-voltage side of the inject capacitor, the IC bias power supply (VDD and GND pins), which is set between 8 V and 16 V, and a remote enable (EN) signal.

Table 2-1 J1 Header Connections
POSITION(1)LABELDESCRIPTION
1 S4 Sense 4 input – connect to a Y-rated sense capacitor, CSEN4
2 S3 Sense 3 input – connect to a Y-rated sense capacitor, CSEN3
3 S2 Sense 2 input – connect to a Y-rated sense capacitor, CSEN2
4 S1 Sense 1 input – connect to a Y-rated sense capacitor, CSEN1
5 GND Ground – connect to the chassis ground of the system with a direct, low-inductance connection
6INJInject output – connect to a Y-rated inject capacitor, CINJ
7 VDD Supply voltage connection – connect to a 12-V bias power supply referenced to GND(2)
8 EN Enable input – leave open or tie high to enable the IC; tie to GND to disable
(1) Pin positions of header J1 are designated left to right when viewed from the top side of the EVM.
(2) Working at an ESD-protected workstation, verify that any wrist straps, bootstraps or mats are connected and referencing the user to Earth ground before power is applied to the EVM.

An 8-pin right-angle header, part number TSW-108-08-G-S-RA, connects the EVM to a corresponding female receptacle, part number SSW-108-01-G-S, which mounts on the EMI filter board that carries the passive filter components – the CM chokes, X-capacitors and Y-capacitors – as well as the sense and inject capacitors. The EVM includes both the header and the receptacle, manufactured by Samtec. See Section 4.2.