SLVUCM6 March   2024 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521923W-Q1 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

3.8 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 3-15 Mask Settings
Register Address Field Name Value Description
Mask effects on device state and nINT pin 0x25 MASK_EFFECT 0x03 no state change, nINT reaction, bit set for Faults
UV Mask 0x24 BUCK1_UV_MASK 0x0 un-masked (Faults reported)
0x24 BUCK2_UV_MASK 0x0 un-masked (Faults reported)
0x24 BUCK3_UV_MASK 0x0 un-masked (Faults reported)
0x24 LDO1_UV_MASK 0x0 un-masked (Faults reported)
0x24 LDO2_UV_MASK 0x0 un-masked (Faults reported)
0x24 LDO3_UV_MASK 0x0 un-masked (Faults reported)
0x24 LDO4_UV_MASK 0x0 un-masked (Faults reported)
Power-up retries/attempts 0x24 MASK_RETRY_COUNT 0x0 Device retries up to 2 times
Die Temperature 0x25 SENSOR_0_WARM_MASK 0x0 un-masked (Faults reported)
0x25 SENSOR_1_WARM_MASK 0x0 un-masked (Faults reported)
0x25 SENSOR_2_WARM_MASK 0x0 un-masked (Faults reported)
0x25 SENSOR_3_WARM_MASK 0x0 un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB) 0x25 MASK_INT_FOR_PB 0x1 masked (nINT pin not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) 0x25 MASK_INT_FOR_RV 0x0 un-masked (nINT pin pulled low for any RV events during transition to ACTIVE state or during enabling of rails)