SLVUCM6 March   2024 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521923W-Q1 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

1 Introduction

The TPS65219-Q1 is a cost and space optimized power management IC (PMIC) that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C communication, GPIOs and configurable multi-function pins. TPS65219-Q1 is characterized for -40°C to +125°C ambient temperature. For safety sensitive applications, TPS65219-Q1 is functional safety capable. Therefore the TPS65219-Q1 development process is a TI-quality managed process, also functional safety FIT rate calculation and failure mode distribution (FMD) is available. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6521923W-Q1.

Note: The NVM configuration described in this document is ideal for the application described below but can also be used to power other processors or SoCs with equivalent power requirements:

  • Processor: AM62x-Q1 (automotive)
  • CORE voltage: 0.75V (up to 3.5A)
  • Memory: LDDR4
  • Input supply (VSYS, PVIN_Bx): 5V