SLVUCM6 March   2024 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521923W-Q1 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

2 PDN and Sequence Diagrams

This section details how the TPS6521923W-Q1 power resources and digital signals are connected to the processor and other peripheral components. Some of the external peripherals, like a uSD card, Ethernet PHY, and HDMI, among others are optional and might not be needed for the end product.