SLVUCM6 March   2024 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521923W-Q1 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

2.1 TPS6521923W-Q1 Sequence and Power Block Diagram

GUID-20240212-SS0I-1CQM-NV6R-PRXWLXT7HSFG-low.svg Figure 2-1 TPS6521923W-Q1 Example Power Block Diagram
GUID-20240212-SS0I-T6GP-ZSVB-BR1PCXJ9F9GP-low.svg Figure 2-2 TPS6521923W-Q1 Power-Up Sequence
Note:
  • tDEGL_EN_Rise_Fast is configurable on the NVM. See register field “EN_PB_VSENSE_DEGL” on the TRM for default value.
  • tREACTION_ON is not configurable. Refer to the specifications table on TPS65219-Q1 data sheet.
GUID-20240212-SS0I-26ZX-VCF1-6PG1MPFCWJ6K-low.svg Figure 2-3 TPS6521923W-Q1 Power-Down Sequence
Note:
  • tDEGL_EN_Fall and tREACTION_OFF are not configurable. Refer to the specifications table on TPS65219-Q1 data sheet.