SLVUCO6 june   2023 TPSI2072-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  6. 2Connection Descriptions
  7. 3Test Equipment
  8. 4Recommended Test Setup
    1. 4.1 Waveforms
    2. 4.2 VS1_ADC and VS2_ADC Voltage Dividers
  9. 5Schematic
  10. 6PCB Layout
  11. 7Interlayer Stitching Capacitor
    1. 7.1 Interlayer Stiching Capacitors & EMI Performance Improvements
    2. 7.2 VS1_ADC and VS2_ADC Voltage Dividers
  12. 8Bill of Materials
  13. 9Revision History

6 PCB Layout

GUID-20230626-SS0I-4P7J-DKT9-CXH9KL5FGLXQ-low.pngFigure 6-1 TPSI2072-Q1 EVM Layer 1
GUID-20230626-SS0I-5HTD-BH5K-HM9K55LJH4SH-low.pngFigure 6-2 TPSI2072-Q1 EVM Layer 2
GUID-20230626-SS0I-CGF2-Z9RV-W8F2WN8CQNBG-low.pngFigure 6-3 TPSI2072-Q1 EVM Layer 3
GUID-20230626-SS0I-0SSD-CPT1-V9BNFQJJF9W3-low.pngFigure 6-4 TPSI2072-Q1 EVM Layer 4
GUID-20230626-SS0I-JGQK-GCM8-MF2T1L8PRPW5-low.pngFigure 6-5 TPSI2072-Q1 EVM Layer 5
GUID-20230626-SS0I-D5MZ-8GRX-G5NTPXVRZLSN-low.pngFigure 6-6 TPSI2072-Q1 EVM Layer 6