SLVUCQ2A july   2023  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
    6. 3.6 Passive vs. Active Solution Comparison
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.4 EVM Performance Validation

  1. Apply a bias supply voltage of 8 V to 16 V (nominal 12 V, with ripple voltage less than 20 mV peak-to-peak) between the VDD and GND terminals of J7. Probe the INJ terminal at header J1 with respect to GND; it should operate at a DC voltage of VVDD/2 and have no AC perturbations that indicate instability. The VDD current consumption should be approximately 12 mA.
  2. The user should perform low-voltage testing prior to connection to a high-voltage power stage. To provide CM excitation, connect a 5-V peak-to-peak square-wave source from a function generator on the regulator-side power connector J6, as shown in Figure 3-4. A 1-nF capacitor in series with the source emulates a practical CM noise source impedance.
    • Using the CM excitation source, verify the dynamic voltage range of the TPSF12C1 INJ pin. Ensure that the INJ pin voltage relative to GND operates in a window between 2.5 V and VVDD – 2 V.
  3. Connect a LISN on the input side at J5 and measure the EMI with AEF disabled (EN jumpered to OFF at J8) to benchmark the existing passive filter. The bottom terminal of inject capacitor can be shorted to GND when AEF is disabled by tying the INJ terminal of J1 to GND. This emulates the Y-capacitor connection in an equivalent passive filter design.
  4. Remove the pulldown short on the inject capacitor and enable the AEF circuit by allowing the EN to float high. Repeat the EMI measurement, thus quantifying the EMI reduction related to AEF circuit operation.
  5. In a similar fashion (but with the LISN replaced by a 50-Ω load connecting from L and N to GND), perform a comparison of filter insertion loss performance using a suitable network analyzer. SMB jacks J2, J3 and J4 on the EVM facilitate signal injection, reference measurement and test measurement, respectively.
  6. Using high-voltage safety precautions, connect the switching power stage as shown in Figure 3-3. Depopulate components R1, R2 and C20 to maximize the clearance spacing from high-voltage nodes to ground adjacent the SMB jacks. Turn the regulator ON and perform EMI measurements with AEF enabled and disabled, similar to the procedure outlined in steps 3 and 4 above.
  7. Turn the regulator OFF. Wait for all high-voltage capacitors to fully discharge.
  8. Power down the IC and remove the VDD supply.