SLVUCS6 August 2024 TPS65987DDK
4.2 PCB Layouts
Figure 4-7 to Figure 4-18 illustrates the TPS65987DDKEVM PCB layers.
Figure 4-7 Top Layer
Figure 4-8 Top Layer Mask
Figure 4-9 Super Speed Layer 2
Figure 4-10 Super Speed Layer 1
Figure 4-11 Power Signal Layer 2
Figure 4-12 Power Signal Layer 1
Figure 4-13 High Speed Layer
Figure 4-14 Ground Plane 3
Figure 4-15 Ground Plane 2
Figure 4-16 Ground Plane 1
Figure 4-17 Bottom Layer
Figure 4-18 Bottom Layer Mask