This section provides a description of the TPS56A37EVM, board layout, and layer illustrations.

The board images are shown in Figure 4-2 and Figure 4-3. The board layouts are shown in Figure 4-4 to Figure 4-8. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS56837 and a large area filled with power ground (PGND). Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. Middle layer 1, Middle layer 2, and the bottom layer are predominantly PGND planes. Analog ground (AGND) area is provided on Middle layer 1. Figure 4-6 shows the AGND and PGND are connected at a single point on the Middle layer 1. The bottom layer contains the output voltage feedback trace, the connection to the VIN pin of the EN control, and the connections of test points.

Figure 4-2 TPS56A37EVM Front Photo

Figure 4-4 Top Assembly

Figure 4-6 Middle Layer 1

Figure 4-8 Bottom Layer

Figure 4-3 TPS56A37EVM Back Photo

Figure 4-5 Top Layer

Figure 4-7 Middle Layer 2