SLVUCV2 September   2024 TPS4HC120-Q1

 

  1.   1
  2.   Description
  3.   3
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Connection Descriptions
      1. 2.1.1 Connections and Test Points
      2. 2.1.2 Jumper Configurations
  9. 3Implementation Results
    1. 3.1 Variable Resistor for CS and CL
      1. 3.1.1 Current Sense Resistor
      2. 3.1.2 Adjustable Current Limit
  10. 4Hardware Design Files
    1. 4.1 TPS4HC120-Q1 Schematic
    2. 4.2 TPS4HC120-Q1 EVM Assembly Drawings and Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks

4.2 TPS4HC120-Q1 EVM Assembly Drawings and Layout

The design of the TPS4HC120-Q1 printed-circuit board (PCB) is shown in Figure 4-2 to Figure 4-5. The EVM is designed using FR4 material, four-layer (2s2p), 2 × 70µm cubic in. top and bottom layers, and 2 × 35µm cubic in. internal plane layers. All components are in an active area on the top side and all active traces to the top and bottom layers to allow the user to easily view, probe, and evaluate. Moving components to both sides of the PCB offers additional size reduction for space-constrained systems.

TPS4HC120EVM TPS4HC120-Q1EVM First Layer (Top View)Figure 4-2 TPS4HC120-Q1EVM First Layer (Top View)
TPS4HC120EVM TPS4HC120-Q1EVM Second Layer GND (Top View)Figure 4-3 TPS4HC120-Q1EVM Second Layer GND (Top View)
TPS4HC120EVM TPS4HC120-Q1EVM Third Layer VCC (Top View)Figure 4-4 TPS4HC120-Q1EVM Third Layer VCC (Top View)
TPS4HC120EVM TPS4HC120-Q1EVM Fourth Layer (Top View)Figure 4-5 TPS4HC120-Q1EVM Fourth Layer (Top View)