SLYU065 March   2023 TMAG6180-Q1 , TMAG6181-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Kit Contents
    2. 1.2 Related Documentation From Texas Instruments
  4. 2Hardware
    1. 2.1 Features
  5. 3Operation
    1. 3.1 Quick Start Setup
    2. 3.2 EVM Operation
      1. 3.2.1 Software Setup
        1. 3.2.1.1 Driver Installation
        2. 3.2.1.2 Firmware
          1. 3.2.1.2.1 Firmware Debug
        3. 3.2.1.3 GUI Setup and Usage
          1. 3.2.1.3.1 Initial Setup
          2. 3.2.1.3.2 GUI Operation
  6. 4Schematics, PCB Layout, and Bill of Materials
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials

3.2 EVM Operation

To use the EVM with the TI-SCB, connect the EVM as shown in Figure 3-1.

GUID-20230315-SS0I-JNJN-NPGK-2KTGZG7KDWPJ-low.svg Figure 3-1 TMAG6180-6181EVM Connected to TI-SCB

The two sensors are mounted opposite from each other at the end of the sensor platform, with TMAG6180-Q1 mounted on the topside and TMAG6181-Q1 mounted on the bottom.

GUID-20230315-SS0I-4NF7-XCGD-6R3ZH7J3X96J-low.svg Figure 3-2 Side Profile of EVM

For use independent of the TI-SCB, a pin map of J1 has been provided on the top layer silk screen.

GUID-20230315-SS0I-VN3L-BCHN-TRXDBJTHLKKK-low.svg Figure 3-3 J1 pin map

Access to 5 V, GND, and 3.3 V are respectively available on pins 2, 4, and 6 of J1. The 5 V input from TI-SCB is provided over USB and is not used to directly power TMAG6180 or TMAG6181. U9 and U10 on TMAG6180-6181EVM accept this input and provide a low noise 5 V AVDD voltage for the ADS8354 (U4) and sensors.

GUID-20230315-SS0I-DRHT-NZX4-Z8T1V2V5S0MF-low.svg Figure 3-4 5 V Supply Circuit

Input to the ADS8354 is controlled using pin 12 (SEL) of J1. The SEL signal sets the output of multiplexor U3 and toggle output control of pin 8 on J1, which is shared between Q1 of TMAG6180 and TURNS on TMAG6181.

Access to the SPI I/O pins of the ADS8354 are available on pins 1,3,5,7 and 9 of J1, also shown in Figure 3-3.

For addtional device testing, probe test pads are provided for COS_P, COS_N, SIN_P, and SIN_N of each device as shown in Figure 3-5.

GUID-20230315-SS0I-DJJD-Z3GX-JFNLXMLB0CDM-low.svg Figure 3-5 Test Pad Locations

The output of the selected device passes through an anti-aliasing filter with an optional active stage. In many cases, this filter is not necessary, but the active stage was included in the reference design for ADS8354 and was used here for congruency.

GUID-20230315-SS0I-WSVQ-FCF9-FWL5FXFKH83Q-low.svg Figure 3-6 ADS8354 with Anti-Aliasing Filter

Full details of the hardware schematic are available in Schematics.