SNAU286 November   2024

 

  1.   1
  2. 1Description
  3. 2Features
  4.   4
  5. 3Evaluation Module Overview
    1. 3.1 Introduction
    2. 3.2 Kit Contents
    3. 3.3 Specifications
  6. 4Implementation Results
    1. 4.1 Evaluation Setup Requirement
    2. 4.2 Setup
      1. 4.2.1 Connection Diagram
      2. 4.2.2 Power Supply
      3. 4.2.3 Clock Output
      4. 4.2.4 EVM Header Configuration
      5. 4.2.5 Configuring the Output Clock Termination
    3. 4.3 Performance Data and Results
      1. 4.3.1 Typical Measurement
  7. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout and Layer Stack-Up
      1. 5.2.1 PCB Layer Stack-Up
      2. 5.2.2 PCB Layout
    3. 5.3 Bill of Materials
  8. 6Additional Information
    1.     Trademarks
  9. 7Related Documentation

4.2.4 EVM Header Configuration

Table 4-2 summarizes the EVM header configurations to connect and route power to the VDD domains of the individual devices, in addition to the individual output enable (OE) or standby pins depending on the device populated.

Table 4-2 EVM Header Configurations
Component Name Description

J6, J11

VDD

VDD Supply Voltage Source

J6: Tie pins 5-6 (default)

J11: Tie pins 3-4 (default)

By default, VDD is sourced from USB power supply and onboard LDO

See Table 4-1 for more details

J10, J12

VDD_Reg

VDD_Reg Voltage Level

Tie pins 1-2 (default):

Selects VDD = 3.3V

Tie pins 3-4:

Selects VDD = 2.5V

Tie pins 5-6:

Selects VDD = 1.8V

J2

DLE/DLN and DLF OE

CDC6C DLF (Y1) OE

Tie pins 1-3 (default):

Pull CDC6CDLF OE to VDD

Tie pins 3-5:

Pull CDC6C DLF (Y1) OE to GND

CDC6C DLE/DLN (Y3) OE

Tie pins 2-4 (default):

Pull CDC6C DLE/DLN (Y3) OE to VDD

Tie pins 4-6:

Pull CDC6C DLE/DLN (Y3) OE to GND

J4

DLX and DLY OE

CDC6C DLX (Y2) OE

Tie pins 1-3 (default):

Pull CDC6C DLX (Y2) OE to VDD

Tie pins 3-5:

Pull CDC6C DLX (Y2) OE to GND

CDC6C DLY (Y4) OE

Tie pins 2-4 (default):

Pull CDC6C DLY (Y4) OE to VDD

Tie pins 4-6:

Pull CDC6C DLY (Y4) OE to GND

J1

VDD_DLF

DLF VDD Supply

Tie pins 1-2 (default):

Connect VDD to CDC6C DLF (Y1)

Leave open:

Disconnect VDD from CDC6C DLF (Y1)

J3

VDD_DLE

DLE/DLN VDD Supply

Tie pins 1-2 (default):

Connect VDD to CDC6C DLE/DLN (Y3)

Leave open:

Disconnect VDD from CDC6C DLE/DLN (Y3)

J7

VDD_DLX

DLX VDD Supply

Tie pins 1-2 (default):

Connect VDD to CDC6C DLX (Y2)

Leave open:

Disconnect VDD from CDC6C DLX (Y2)

J8

VDD_DLY

DLY VDD Supply

Tie pins 1-2 (default):

Connect VDD to CDC6C DLY (Y4)

Leave open:

Disconnect VDD from CDC6C DLY (Y4)