SNAU296 December   2023 LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EVM Quick Start
  6. 3EVM Configuration
    1. 3.1  Power Supply
    2. 3.2  Logic Inputs and Outputs
    3. 3.3  Switching Between I2C and SPI
    4. 3.4  Generating SYSREF Request
    5. 3.5  XO Input
      1. 3.5.1 48-MHz TCXO (Default)
      2. 3.5.2 External Clock Input
      3. 3.5.3 Additional XO Input Options
      4. 3.5.4 APLL Reference Options
    6. 3.6  Reference Clock Inputs
    7. 3.7  Clock Outputs
    8. 3.8  Status Outputs and LEDs
    9. 3.9  Requirements for Making Measurements
    10. 3.10 Typical Phase Noise Characteristics
  7. 4EVM Schematics
    1. 4.1  Power Supply Schematic
    2. 4.2  Alternative Power Supply Schematic
    3. 4.3  Power Distribution Schematic
    4. 4.4  LMK5C33414A and Input References IN0 to IN3 Schematic
    5. 4.5  Clock Outputs OUT0 to OUT3 Schematic
    6. 4.6  Clock Outputs OUT4 to OUT9 Schematic
    7. 4.7  Clock Outputs OUT10 to OUT13 and Clock Inputs IN2 and IN3 Schematic
    8. 4.8  XO Schematic
    9. 4.9  Logic I/O Interfaces Schematic
    10. 4.10 USB2ANY Schematic
  8. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  9. 6Appendix A - TICS Pro LMK5C33414A Software
    1. 6.1  Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2  Using the Status Page
    3. 6.3  Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4  Using APLL1, APLL2, and APLL3 Pages
      1. 6.4.1 APLL DCO
    5. 6.5  Using the DPLL1, DPLL2, and DPLL3 Pages
    6. 6.6  Using the Validation Page
      1. 6.6.1 DPLL DCO
    7. 6.7  Using the GPIO Page
    8. 6.8  SYNC/SYSREF/1-PPS Page
    9. 6.9  Using the Outputs Page
    10. 6.10 EEPROM Page
    11. 6.11 Design Report Page

6.3.1 Cascaded Configurations

Cascaded configurations can be created using the input page, where the relevant VCO buffers and dividers are automatically enabled by inferring the state of source selection registers.

At least one PLL must always be active and set to XO reference source for cascaded configurations to be valid. APLL start-up priority automatically chooses XO-source APLLs to start up before all other PLLs whenever possible. Start-up priority cannot be properly inferred, therefore users must set this priority themselves in the User Controls page if in pin-selection mode. In the example image below, APLL3 is referenced to XO input and APLL1 and APLL2 are referenced from APLL3. Priority is controlled in ascending order, with 0 first and 2 last. APLLs can share priorities; if all APLL priorities are set to 0, all APLLs start up simultaneously.

GUID-20231205-SS0I-ZZ2T-VZMC-1S9D7K4QBFVF-low.png Figure 6-11 Cascade APLL Start Priorities