SNAU310 June   2024 LMKDB1102 , LMKDB1202

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2EVM Quick Start
    1. 2.1 Setup
    2. 2.2 EVM Measurements
  8. 3Hardware
    1. 3.1 EVM Configuration
      1. 3.1.1 Power Supply
      2. 3.1.2 Logic Input and Outputs
      3. 3.1.3 Clock Input
      4. 3.1.4 Clock Outputs
      5. 3.1.5 Status Outputs, LEDs, and Test Points
  9. 4Implementation Results
    1. 4.1 Typical Phase Noise Characteristic
  10. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 LMKDB1102EVM Bill of Materials (BOM)
    4. 5.4 LMKDB1202EVM Bill of Materials (BOM)
  11. 6Compliance Information
    1. 6.1 Compliance and Certifications
  12. 7Additional Information
    1. 7.1 Trademarks
  13. 8References

3.1.2 Logic Input and Outputs

The logic input and output pins on LMKDB1102 and LMKDB1202 provides option for output active / inactive control, loss of signal (LOS) detection, and output impedance selection. LMKDB1202 offers an additional input clock selection pin, CLKIN_SEL_tri.

Table 3-2 Clock Input Selection (only for LMKDB1202)
CLKIN_SEL_tri Input LevelFunction
Low (default)CLKIN0 is the input source for all outputs.
HighCLKIN1 is the input source for all outputs.
Hi-ZCLKIN0 is the input source for OUT1 outputs and CLKIN1 is the input source for OUT2 outputs.
Table 3-3 Output Enable Pin Control
OE1# and OE2# Input Level OUTPUT STATUS
Low (default)Active
HighInactive
Table 3-4 Loss of Signal (LOS) Detection (Status pin)
LOSb OUTPUT LEVELLOS STATUS
LowNot detected
HighDetected
Table 3-5 LP-HCSL Differential CLock Output Impedance Select
ZOUT_SEL Input LevelFunction
Low (default)LMKDB1x02 has 85Ω output termination
HighLMKDB1x02 has 100Ω output termination