SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

4.5 Resolution Readback Example

This example configures the DS90Ux947-Q1 serializer to allow for measuring the detected active video dimensions at the DS90Ux948-Q1 deserializer during operation. This feature can be used to detect a video transmission error by comparing the expected active resolution against the detected resolution. Note that this feature should only be used during system statup, and should not be left permenantly enabled during normal operation. Enabling this feature will disable the use of the LOCK pin as a link indicator, and will cause one white pixel to appear randomly in the video output for one frame at the time of enabling/disabling. For this reason it is best to enable this readback feature during system startup before the display backlight has been enabled, to avoid visual disruption.

Configuration Sequence

  1. Check the recovered active horizontal and vertical frame dimensions.
    1. Write 0x09 to address 0x68 PGDBG (Table 3-2) to select active horizontal LSB and trigger an update of the test mux data.
    2. Read 0x69 PGTSTDAT (Table 3-2) and record bits [5:0] as "AHL".
    3. Write 0x19 to address 0x68 PGDBG (Table 3-2) to select active horizontal MSB and trigger an update of the test mux data.
    4. Read 0x69 PGTSTDAT (Table 3-2) and record bits [5:0] as "AHM".
    5. Write 0x29 to address 0x68 PGDBG (Table 3-2) to select active vertical LSB and trigger an update of the test mux data.
    6. Read 0x69 PGTSTDAT (Table 3-2) and record bits [5:0] as "AVL".
    7. Write 0x39 to address 0x68 PGDBG (Table 3-2) to select active horizontal MSB and trigger an update of the test mux data.
    8. Read 0x69 PGTSTDAT (Table 3-2) and record bits [5:0] as "AVM".
    9. Calculate active horizontal pixels [11:0] = [AHM:AHL] (Table 3-2) (for example, AHM = 011110b, AHL = 000000b, Active horizontal pixels = 011110000000b = 0x780 = 1920 pixels).
    10. Calculate active vertical pixels [11:0] = [AVM:AVL] (Table 3-2) (for example AVM = 010000b, AVL = 111000b, Active horizontal pixels = 010000111000b = 0x438 = 1080 pixels).
  2. Compare measured active horizontal and vertical pixel dimensions to expected values for the external video source attached to the serializer side.

  3. Disable readback features

    1. Write 0x00 to address 0x68