SNLA293 May 2022 DP83TC811R-Q1 , DP83TC811S-Q1
Test Mode | Parameter Under Test | MMD | Register | Value |
---|---|---|---|---|
Test Mode 1 | Transmit Droop | 0x01 | 0x0904 | 0x2001 |
Test Mode 2 | MASTER transmit jitter | 0x01 | 0x0904 | 0x4001 |
Test Mode 4 | Transmit Distortion | 0x01 | 0x0904 | 0x8001 |
0x1F | 0x0462 | 0x0011 | ||
Test Mode 5 | Transmit PSD | 0x01 | 0x0904 | 0xA001 |
- | SLAVE transmit jitter | 0x1F | 0x0462 | 0x0011 |
TX_TCLK (66.66MHz) is needed for Trasnmit Distortion and SLAVE transmit jitter testing. The clock is programmed to be transmitted on LED_0 using the write reg<0x0462> = 0x0011.