SNLA448 November   2023 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Test Setup
  6. 3Test Procedure
  7. 4Explanation of TI's PCIe Compliance Tool
  8. 5LMK3H0102 Test Results
    1. 5.1 LMK3H0102 Test Results Summary
    2. 5.2 PCIe Tool Input File Waveforms for the LMK3H0102 Family
    3. 5.3 LMK3H0102 Detailed Jitter Measurements
  9. 6Summary
  10. 7References

5.1 LMK3H0102 Test Results Summary

Table 5-1 is the PCIe compliance results summary for the LMK3H0102 100-MHz LP-HCSL no SSC phase noise measurement. Figure 5-1 displays the phase noise capture used for the analysis.Table 5-2 is the PCIe compliance results summary for the LMK3H0102 100-MHz LP-HCSL –0.5% down-spread SSC phase noise measurement. Figure 5-2 displays the phase noise capture used for the analysis. The jitter compliance of the device for PCIe Gen 1 through 6, noise folds 0 and 3, and clock architectures Common Clock with Spread (CCS) and Separate Reference Independent Spread (SRIS) is displayed.

A PCIe jitter spec or time domain calculation can have one of the following statuses:

  • PASS: within specifications/limits
  • FAIL: outside specifications/limits
  • N/A: no specifications/limits available
Table 5-1 Frequency Domain LMK3H0102 PCIe Tool Test Results Summary, No SSC
Jitter Filter Clock Arch. Noise Fold Min (ps) Max (ps) Limit Status
PCIe1(1) CC 0 0.0 2.202 86 ps pp PASS
3 0.0 2.27 86 ps pp PASS
PCIe2 CC 0 0.053 0.273 3.1 ps RMS PASS
3 0.101 0.279 3.1 ps RMS PASS
SRNS 0 0.095 0.216 N/A N/A
3 0.146 0.225 N/A N/A
PCIe3 CC 0 0.024 0.082 1 ps RMS PASS
3 0.041 0.084 1 ps RMS PASS
SRNS 0 0.249 0.067 N/A N/A
3 0.273 0.07 N/A N/A
PCIe4 CC 0 0.024 0.082 0.5 ps RMS PASS
3 0.041 0.084 0.5 ps RMS PASS
SRNS 0 0.17 0.067 N/A N/A
3 0.18 0.07 N/A N/A
PCIe5 CC 0 0.004 0.036 0.15 ps RMS PASS
3 0.004 0.037 0.15 ps RMS PASS
SRNS 0 0.052 0.029 N/A N/A
3 0.053 0.030 N/A N/A
PCIe6 CC 0 0.004 0.020 0.10 ps RMS PASS
3 0.008 0.020 0.10 ps RMS PASS
SRNS 0 0.036 0.017 N/A N/A
3 0.039 0.018 N/A N/A
Table 5-2 Frequency Domain LMK3H0102 PCIe Tool Test Results Summary, –0.5% Down-Spread SSC
Jitter FilterClock Arch.Noise FoldMin (ps)Max (ps)LimitStatus
PCIe1(1)CCS00.03.88686 ps ppPASS
30.04.65486 ps ppPASS
PCIe2CCS00.0530.1613.1 ps RMSPASS
30.1010.3123.1 ps RMSPASS
SRIS00.0950.169N/AN/A
30.1460.334N/AN/A
PCIe3CCS00.0240.0781 ps RMSPASS
30.0410.1011 ps RMSPASS
SRIS00.2490.289N/AN/A
30.2730.376N/AN/A
PCIe4CCS00.0240.0780.5 ps RMSPASS
30.0410.1010.5 ps RMSPASS
SRIS00.170.185N/AN/A
30.180.217N/AN/A
PCIe5CCS00.0040.0310.15 ps RMSPASS
30.0040.040.15 ps RMSPASS
SRIS00.0520.066N/AN/A
30.0530.072N/AN/A
PCIe6CCS00.0040.0160.10 ps RMSPASS
30.0080.0240.10 ps RMSPASS
SRIS00.0360.047N/AN/A
30.0390.05N/AN/A
  1. PCIe1 is measured using peak-to-peak jitter instead of RMS jitter using a conversion ratio of 8.83, as specified by the PCIe standard.

Table 5-3 is the PCIe compliance summary for the LMK3H0102 time domain analysis which demonstrates the time domain compliance of the device.

Table 5-3 Time Domain LMK3H0102 PCIe Tool Test Results Summary
CalculationMinAvgMaxLimitStatus
Vcross396.62 mV407.61 mV416.73 mV250 mV to 550 mVPASS
Vhigh720 mV720 mV150 mVPASS
Vlow-12.0 mV-12.0 mV–150 mVPASS
Period9.9 ns9.996 ns10.1 ns9.847 ns to 10.203 nsPASS
Duty Cycle50.02%50.58%51.021%40% to 60%PASS
Overshoot Voltage28.26 mV40.0 mV300 mVPASS
Undershoot Voltage-32.28 mV-48.0 mV–300 mVPASS
Rising Edge Rate2.24 V/ns2.584 V/ns2.92 V/ns0.6 V/ns to 0.4 V/nsPASS
Falling Edge Rate2.12 V/ns2.612 V/ns3.08 V/ns0.6 V/ns to 0.4 V/nsPASS