Table 1. DS90UR910-Q1 Configuration Modes

7.3.1 Input Receive Equalization

The input equalizer of the DS90UR910-Q1 is designed to compensate the attenuation distortion results from cable of different length or wire gauge. The equalizer gain setting is controlled by the control pins EQ[3:1] or through register programming. Users can optimize the equalizer’s gain setting along with the de-emphasis level of the DS90UR90xQ to achieve the optimum jitter performance.

Note this function cannot be seen at the RIN± input but can be observed at the serial test port (CMLOUT±) enabled through the serial bus control registers. The equalization feature may be controlled by the external pin or by register.

7.3.2 CSI-2 Interface

The DS90UR910-Q1 (in default mode) takes the RGB data bits R[7:0], G[7:0] and B[7:0] defined in the 24-bit serializer pinout and directly maps to the RGB888 color space in the data frame. The DS90UR910-Q1 follows the general frame format (see Figure 11). Upon the end of the vertical sync pulse (VS), the DS90UR910-Q1 generates the frame end and frame start synchronization packets within the vertical blanking period. The timing of the frame start does not reflect the timing of the VS signal.

Upon the rising edge of the DE signal, each active line is output in a long data packet with the RGB888 data format. At the end of each packet, the data lanes DATA0± and DATA1± return to the LP-11 state, while the clock lane CLK± continue outputting the high-speed clock.

Figure 11. General Frame Format

7.3.3 High-Speed Clock and Data

The high-speed clock and data outputs are source synchronous interface. The half rate clock at CLK± is derived from the pixel clock sourced by the clock or data recovery circuit of the DS90UR910-Q1. The clock frequency is 6 times the pixel clock frequency. The 24-bit recovered RGB data is serialized and output at the 2 high-speed data lanes DATA0± and DATA1± in according to the CSI-2 protocol. The data rate of each lane is 12 times the pixel clock. As an example, at a pixel clock of 75 MHz, the CLK± runs at 450 MHz, and the data lanes run at
900 Mb/s.

The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample data at the rising and falling edges of the clock. Figure 3 shows the timing relationship of the clock and data lines. The DS90UR910-Q1 supports continuous high-speed clock.

High-speed data are sent out at DATA0± and DATA1± in bursts. In between data bursts, the data lanes return to low power states in according to protocol defined in D-PHY standard. The rising edge of the differential clock (CLK+ – CLK–) is sent during the first payload bit of a transmission burst in the data lanes.

The DS90UR910-Q1 recovers the data bits R[7:0], G[7:0], B[7:0], VS, HS and DE from the serial FPD-Link II bit stream at RIN±. During the vertical blanking period (VS goes low), it sends the short frame end packet, followed by a short frame start packet. User can program the time between frame end to frame start packets from 0 to (2¹⁶–1) in units of 8 × pclk_period / 3.

7.3.4 Data Frame RGB Mapping

Table 3 shows the pixel data R[7:0], G[7:0 and B[7:0] defined in DS90UR90xQ and DS90Ux92x serializers pinout, which are recovered by the DS90UR910-Q1 and output in RGB888 format (data type 0x24) at the CSI-2 interface.

Figure 12. DATA0± and DATA1± Packet Format in According to CSI-2 Protocol for RGB888

7.3.5 Display Timing Requirements

Table 5 shows the supported display resolutions for the DS90UR910-Q1. The display timings assume an estimated overall blanking rate of 1.2. The DS90UR910-Q1 automatically detects the incoming data rate by from the frame rate (by measuring VS). This timing is then mapped into a look up table. The lookup table is used for any pixel rate of PCLK from 10 MHz to 65 MHz. The limitation that it assumes the frame rate is 60 fps and
30 fps. An override option is available to set each of the parameter individually for a data rate that is not listed in the table. Option is programmed through CCI. Operation of frequencies above 65 MHz require additional I2C or CCI programming of CSI_TIMING registers.

7.4.1 Ultra-Low Power State

DS90UR910-Q1 D-PHY lanes enters ULPS mode upon software standby mode through Camera Control Interface (CCI) generated by application processor. When ULPS is entered, all lanes including the clock and data lanes are put in ULPS according to the MIPI D-PHY protocol. D-PHY can reduce power consumption by entering ULPS mode.

Ultra-low power state entry command is sent after an escape mode entry command through CCI, and then lane shall enter the Ultra-Low Power State (ULPS). When ULPS is entered, all lanes including the clock and data lanes are put in ULPS according to the MIPI DPHY protocol. Typically an ULPS entry command is used but other sequences can be used also. ULPS is exited by means of a mark-1 state with a length TWAKEUP followed by a stop state.

Figure 13. Ultra-Low Power State

7.4.2 Non-Continuous or Continuous Clock

DS90UR910-Q1 D-PHY supports continuous clock mode and non-continuous clock mode. Default mode is non-continuous clock mode, where the clock lane enters in LP mode between the transmissions of data packets. Non-continuous clock mode is only non-continuous during the vertical blanking period for lower PCLK rates. For higher PCLK rates, the clock is non-continuous between line and frame packets. Operating modes are configurable through CCI.

Clock lane enters LP11 during horizontal blanking if the horizontal blanking period is longer than the overhead time to start or stop the clock lane. There is auto-detection of the length of the horizontal blank period. The threshold is 70 PCLK cycles. Register bit available to disable off the non-continuous clock mode.

7.5.1 Serial Control Bus (CCI or I2C)

The DS90UR910-Q1 can be configured by the use of the CCI or I2C as defined by MIPI, which is a bi-directional, half-duplex, serial control bus consists of SCL and SDA. The SDA is the bi-directional data line. The SCL is the serial clock line. Both SCL and SDA are driven by open drain drivers and required external pullup resistors to VDDIO. The signals are either driven low or pulled high.

The DS90UR910-Q1 is a CCI slave. ID[1:0] pins select one of the four CCI slave addresses (see Table 6).

The serial bus protocol is initiated by START or START-REPEATED, and terminated by STOP condition. A START occurs when SDA transitions low while SCL is high. A STOP occurs when SDA transitions high when SCL is high (see Figure 14).

Figure 14. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the 7-bit slave address followed by a write-bit (0), and listens for a response from the slave. This response is referred to as an acknowledge bit. If the slave on the bus is addressed correctly, it acknowledges the master by driving the SDA low (ACK). If the address does not match the slave address of the device, it negative acknowledges the master by letting SDA be pulled high (NACK). In a write operation from master to slave, the master sends the 8-bit index address of the register that it wants to access. After the slave ACKs, the master sends the 8-bit data byte. The slave ACKs after each data byte is successfully received and is ready to receive another byte into the next sequential index location. At the end of the data transfer, the master ends the transaction with a STOP condition.

In a read operation, the master first sends the 8-bit index address of the register that it wants to access. After receiving an ACK from the slave, it initiates a START-REPEAT condition, sends the 7-bit slave address followed by the read-bit (1). The slave ACKs and sends out the 8-bit data byte. The master acknowledges an ACK when another data byte is sent to the next sequential index address. The master acknowledges an NACK when no more data byte is sent, and ends the transaction with a STOP condition.

The CCI interface of the DS90UR910-Q1 supports standard mode (<100 kHz) or fast mode (<400 kHz) with 8-bit index addressing and 8-bit data transfer. It supports the following read or write operations between the DS90UR910-Q1 and the CCI master:

• Single read from random location
• Single read from current location
• Sequential read starting from a random location
• Sequential read starting from the current location
• Single write to a random location
• Sequential write starting from a random location

Figure 15. I2C or CCI Read or Write Operations

Table 7. Serial Bus Control Registers