SNLU278 March 2021 DS160PR412 , DS160PR421
Table 5-1 lists the CHANNEL registers. All register offset addresses not listed in Table 5-1 should be considered as reserved locations and the register contents should not be modified.
Note that the register offset is provided for the channel 0 or channel 2 registers (channel bank 0 or channel bank 1). For the channel 1 registers on the channel bank 0 (or the channel3 on the channel bank 1), add 0x20 to the provided offset.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | RX_DET_STS | Receiver Detect Status Register | Go |
0x1 | EQ_CTRL | Equalizer Control Register | Go |
0x2 | GAIN_CTRL | DC Gain and VOD Control Register | Go |
0x3 | RX_DET_CTRL1 | Receiver Detect Control Register 1 | Go |
0x9 | RX_DET_CTRL2 | Receiver Detect Control Register 2 | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read only access. |
Write Type | ||
R/W | R/W | Read / Write access. |
Reset or Default Value | ||
-n | Value after reset or the default value. |
RX_DET_STS is shown in Table 5-3.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | rx_det_comp_p | R | 0x0 | Rx Detect Positive Polarity Status: 0: Not detected 1: Detected The value is latched. |
6 | rx_det_comp_n | R | 0x0 | Rx Detect Negative Polarity Status: 0: Not detected 1: Detected The value is latched. |
5 | RESERVED | R | 0x0 | Reserved |
4 | RESERVED | R | 0x0 | Reserved |
3 | RESERVED | R | 0x0 | Reserved |
2 | RESERVED | R | 0x0 | Reserved |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |
EQ_CTRL is shown in Table 5-4.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | eq_en_bypass | R/W | 0x0 | Enable CTLE Stage 1 Bypass: |
5 | eq_bst1_2 | R/W | 0x0 | CTLE Boost Stage 1 Control. |
4 | eq_bst1_1 | R/W | 0x0 | See MSB |
3 | eq_bst1_0 | R/W | 0x1 | See MSB |
2 | eq_bst2_2 | R/W | 0x0 | CTLE Boost Stage 2 Control. |
1 | eq_bst2_1 | R/W | 0x0 | See MSB |
0 | eq_bst2_0 | R/W | 0x1 | See MSB |
GAIN_CTRL is shown in Table 5-5.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | RESERVED | R | 0x0 | Reserved |
4 | RESERVED | R | 0x0 | Reserved |
3 | RESERVED | R | 0x0 | Reserved |
2 | eq_hi_gain | R/W | 0x0 | Set CTLE DC Gain: |
1 | drv_sel_vod_1 | R/W | 0x1 | TX VOD Select: |
0 | drv_sel_vod_0 | R/W | 0x1 | See MSB |
RX_DET_CTRL1 is shown in Table 5-6.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | RESERVED | R | 0x0 | Reserved |
4 | RESERVED | R | 0x0 | Reserved |
3 | RESERVED | R | 0x0 | Reserved |
2 | mr_rx_det_man | R/W | 0x0 | Manual override of rx_detect. |
1 | en_rx_det_count | R/W | 0x0 | Enable RX detect valid counter. |
0 | sel_rx_det_count | R/W | 0x0 | Select valid detect count before enable: |
RX_DET_CTRL2 is shown in Table 5-7.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | RESERVED | R | 0x0 | Reserved |
4 | RESERVED | R | 0x0 | Reserved |
3 | RESERVED | R | 0x0 | Reserved |
2 | mr_rx_det_rst | R/W | 0x0 | RX Detect Reset |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |