SNLU293A December   2022  – December 2022 DS560DF810

 

  1.   DS560DF810EVM User's Guide
  2.   Trademarks
  3. 1Hardware Description and Setup
    1. 1.1 Required Hardware
    2. 1.2 General Hardware Test Setup Procedure
    3. 1.3 Hardware Configuration to use Onboard 25 MHz Oscillator for CAL_CLK_IN
  4. 2Software Description
    1. 2.1 Software Installation Sequence
    2. 2.2 Latte Functional Overview
    3. 2.3 Useful Latte Short-Cuts
    4. 2.4 DS560DF810EVM Initialization Through the Latte GUI
      1. 2.4.1 Connect Latte to Board
      2. 2.4.2 Compile Libraries
      3. 2.4.3 Example: Programming DS560DF810EVM for 26.5625 GBd PAM4 Test Case
      4. 2.4.4 Retimer Configuration
      5. 2.4.5 Retimer “Useful Functions” (Contained in the usefulFunctions.py Latte Script)
      6. 2.4.6 Vertical Eye Monitor
  5. 3Test Case Examples
    1. 3.1 Transmitter Test Case – EVM Board Output Evaluation for 26.5625 GBd PAM4 Data
    2. 3.2 Receiver Test Case – High Loss Input Channel to Retimer EVM, 26.5625 GBd PAM4
  6. 4Supplemental Documents
  7. 5EVM Cable Assemblies
  8. 6Revision History

1.2 General Hardware Test Setup Procedure

  1. Check the EVM jumper settings to ensure they match Figure 1-1.

  2. Connect a 5 V power supply to the power jack (PWR_JACK), connector J26 on the DS560DF810EVM board.

  3. Check the DS2 (PWR) LED. The LED light should be on.

  4. Connect the USB Type Mini-B Cable from PC to the USB port (J1) of the EVM.

  5. Check the DS4 (USB_PWR) LED.

  6. The 5 V voltage is regulated down to 3.3 V on the EVM (refer to Figure 1-2).

    • The 3.3 V supply is used to derive the 1.2 V and 1.8 V rails for the DS560DF810 retimer.

    • In addition, the 3.3 V voltage directly powers up the EEPROM, FTDI USB interface chip and level shifter devices.

    • VDD 1.2 V is powered up first and secondly the VDD 1.8 V.

    • VDD 1.2 V uses DC-DC regulator, while the VDD 1.8 V regulation is done through LDO.

  7. Check the DS1 LED (3.3 V) to confirm it is on.

  8. The default EVM jumper settings are for using external CAL_CLK_IN signal. If using this setup case, connect the external clock signal to the retimer CAL_CLK_IN pin through the board connector J100.

Recommended CAL_CLK_IN external signal characteristics

  • 1.8 V LVCMOS compatible clock or sinusoidal signal

  • 25 MHz frequency ± 100 PPM

Figure 1-2 DS560DF810EVM Power Tree