SNLU297 May   2021 DS320PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1  DS320PR810 5-Level I/O Control Inputs
    2. 2.2  DS320PR810 Modes of Operation
    3. 2.3  DS320PR810 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR810 Equalization Control
    5. 2.5  DS320PR810 RX Detect State Machine
    6. 2.6  DS320PR810 DC Gain Control
    7. 2.7  DS320PR810 EVM Global Controls
    8. 2.8  DS320PR810EVM Downstream Devices Control
    9. 2.9  DS320PR810EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus Slave Mode)
  4. 3Test Setup and Results
  5. 4Schematics
  6. 5Board Layout
  7. 6Bill of Materials
  8. 7References

2.4 DS320PR810 Equalization Control

Each channel of the DS320PR810 features a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. Table 2-4 shows available equalization boost through EQ control pins (EQ1_0 and EQ0_0 for channels 0–3 and EQ1_1 and EQ0_1 for channels 4–7) when in Pin Control mode (MODE = L0).

Table 2-4 Equalization Control Settings
EQ INDEX EQ1 PIN LEVEL EQ0 PIN LEVEL CTLE BOOST AT 8 GHz (dB) CTLE BOOST AT 16 GHz (dB)
0 L0 L0 0 0
1 L0 L1 1.2 2.0
2 L0 L2 2.4 4.0
3 L0 L3 3.6 6.0
4 L0 L4 4.8 8.0
5 L1 L0 5.6 10.0
6 L1 L1 6.2 11.0
7 L1 L2 6.9 12.0
8 L1 L3 7.5 13.0
9 L1 L4 8.1 14.0
10 L2 L0 8.7 15.0
11 L2 L1 9.1 16.0
12 L2 L2 9.4 17.0
13 L2 L3 10.0 18.0
14 L2 L4 10.8 19.0
15 L3 L0 11.2 20.0
16 L3 L1 12.0 21.0
17 L3 L2 12.8 22.0
18 L3 L3 13.2 23.0
19 L3 L4 14.0 24.0

The equalization gain of each channel of each device can also be set by writing to SMBus, I2C registers in I2C Mode. Refer to the DS320PR810 Programming Guide for details.