SNOAAA7 April   2024 LMG3522R030

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Overview of Inverter Model
    1. 2.1 Power Stage
    2. 2.2 Control and Modulation Method
  6. 3Realization of Digital Control Using C-Script Block
    1. 3.1 Overview of Project Structure
    2. 3.2 AC Voltage Sampling and True RMS Value Calculation
    3. 3.3 Multiple Loop Control
      1. 3.3.1 Voltage Loop With Notch Filter
      2. 3.3.2 Current Loop With PI Compensator Anti-Windup
      3. 3.3.3 Sinusoidal and Sawtooth Wave Generator
      4. 3.3.4 Totem-Pole Modulation and Dead-Time Control
  7. 4Simulation Results
  8. 5Summary
  9. 6References

4 Simulation Results

This section presents simulation results to verify the theory and code implementation. See Table 2-1 for the power stage parameters.

During the start-up process, to avoid a voltage surge, the initial value of the RMS array is set to 70. From start-up to 95% of the final value is defined as the settle time. Figure 4-1 shows low-frequency bridge switches at 50Hz, and high-frequency bridge switches at 100kHz. In the zero crossing, some glitches happened because of the error signal, this can be undermined by increasing the threshold.

From start-up to 95% of the final value, 660ms is required. To better evaluate the performance of control parameters, a series of transient tests are set. As illustrated during the full-load and half-load situation, inductor current is a relatively standard sine wave. However, under light load, the inductor current exhibits obvious distortion. One effective way to decrease the distortion is to increase the inductance.

From Table 4-1, THD% and setting time indicate that the control system can regulate the inductor current and output voltage quickly and effectively.

GUID-20240319-SS0I-BN2F-30NF-94MVJJKD7T2X-low.png
HF HS: High frequency and High Side PWM signals
HF LS: High frequency and Low Side PWM signals
LF HS: Low frequency and High Side PWM signals
LF LS: Low frequency and Low Side PWM signals
Figure 4-1 Start-Up Process
GUID-20240320-SS0I-FMF9-BB5M-GBMFH819SQ5T-low.png Figure 4-2 Load Transient (100% to 50% to 10%)
GUID-20240319-SS0I-VQTN-NWST-T1WVF48MXRC1-low.png Figure 4-3 Load Transient (50% to 100% to 50%)
GUID-20240319-SS0I-VWDM-VVXD-JZLXGBV9QTJQ-low.png Figure 4-4 True RMS Calculation in Load Transient
Table 4-1 THD% and Settle Time
Condition THD% Settle Time
Full load start-up 2.7% 0.660s
Full load to half-load 2.8% 0.281s
Half-load to 10%-load 2.6% 0.259s

Figure 4-4 shows the output of true RMS calculation block. Note the trade-off in this block. A larger array number slows the calculation and adds additional delay to the system. This causes the output voltage to exceed the reference value because the RMS calculation lags behind the actual value. However, a short array length brings a 50Hz frequency ripple into the RMS value, which causes oscillation in the control. After many tests, a window width of 4 was found to be a good value in this model.