SNVAA80 July   2024 LM5177 , LM51770

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Reverse Current Operation
  6. 3Design Considerations
  7. 4Pin Configurations
    1. 4.1 Other Pin Configurations
      1. 4.1.1 MODE Pin
      2. 4.1.2 IMONOUT
  8. 5Application Measurements
  9. 6Summary
  10. 7References

3 Design Considerations

Figure 3-1 shows the block diagram for reverse current operation. There are certain considerations to operate the LM5177 to operate in the reverse direction.

LM5177, LM5177X Block Diagram for Reverse Current Operation Figure 3-1 Block Diagram for Reverse Current Operation

If the device is used in a Backup System, charging needs to be limited once a defined voltage level is reached. A possible implementation is shown in Figure 3-2

LM5177, LM5177X Block Diagram for Reverse CV Regulation Using MODE Pin Control Figure 3-2 Block Diagram for Reverse CV Regulation Using MODE Pin Control

The TLV431 shunt regulator is used to stop charging on the defined maximum charge voltage level. An additional PNP Transistor is used to adjust the logic level of the MODE signal. When the biasing at the Vref pin of the TLV431 reaches 1.24V, the pin conducts and pulls the MODE pin low and puts the LM5177 into PSM mode which stops charging.

The resistors in the voltage divider must have high resistance to limit the reference current of the TLV431 and reduce power loss.

The storage element can be any type, such as batteries, capacitors, or super-capacitors. In this application note, dielectric capacitors are used as the storage element. In the design illustrated in Figure 3-2, the VCC voltage is 5V with a maximum supply current of 3A and the storage element charges to a constant voltage of 13.1V. This charging limit can be adjusted by changing the ratio of the voltage divider circuit. When the storage voltage reaches the desired voltages, the reference voltage from the voltage divider circuit rises to 1.24V, causing the cathode voltage of the TLV431 to drop from VCC to 1.8V.

When the cathode voltage decreases, the voltage forward biases the emitter-to-base terminals of the PNP transistor, which then lowers the emitter-to-collector voltage. This causes the gate-to-source voltage of the N-channel MOSFET to rise from 0V to VCC, turning the MOSFET on. As a result, the MODE pin voltage drops from VCC to 20mV. This change prompts the buck-boost controller to switch from FPWM mode to PSM mode, causing the storage to discharge. The discharging continues until the battery voltage hits the negative threshold of the hysteresis control. This process allows the storage voltage to stabilize around 13.1V, with minor fluctuations due to the switching delay of the MOSFET.